ADS5287IRGCRG4 Datasheet, PDF (15/42 Pages) Texas Instruments – 10-Bit, Octal-Channel ADC Up to 65MSPS

ADS5287
www.ti.com
SBAS428D – JANUARY 2008 – REVISED JUNE 2012
SERIAL REGISTER MAP
Table 3. SUMMARY OF FUNCTIONS SUPPORTED BY SERIAL INTERFACE^{(1) (2) (3) (4)}
ADDRESS
IN HEX D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
NAME
DESCRIPTION
DEFAULT
00
X
RST
Self-clearing software RESET.
Inactive
XXXXXXXX
PDN_CH<8:1>
Channel-specific ADC power-
down mode.
Inactive
X
PDN_PARTIAL
Partial power-down mode (fast
recovery from power-down).
Inactive
0F
X
PDN_COMPLETE
Register mode for complete
power-down (slower recovery).
Inactive
X
PDN_PIN_CFG
Configures the PD pin for partial Complete
power-down mode.
power-down
11
X
X XX
XXX
LVDS current drive
X X X ILVDS_LCLK<2:0> programmability for LCLK_N and
LCLK_P pins.
3.5mA drive
ILVDS_FRAME
<2:0>
LVDS current drive
programmability for ADCLK_N and 3.5mA drive
ADCLK_P pins.
ILVDS_DAT<2:0>
LVDS current drive
programmability for OUT_N and
OUT_P pins.
3.5mA drive
EN_LVDS_TERM
Enables internal termination for
LVDS buffers.
Termination
disabled
1
12
1
1
14
X
X
X
TERM_LCLK<2:0>
Programmable termination for
LCLK_N and LCLK_P buffers.
Termination
disabled
XXX
TERM_FRAME
<2:0>
Programmable termination for
ADCLK_N and ADCLK_P buffers.
Termination
disabled
X XX
TERM_DAT<2:0>
Programmable termination for
OUT_N and OUT_P buffers.
Termination
disabled
XXXXXXXX
LFNS_CH<8:1>
Channel-specific, low-frequency
noise suppression mode enable.
Inactive
24
X
X
X
X
X
X
X
X
INVERT_CH<8:1>
Swaps the polarity of the analog
input pins electrically.
IN_P is
positive
input
X00
EN_RAMP
Enables a repeating full-scale
ramp pattern on the outputs.
Inactive
0X0
DUALCUSTOM_
PAT
Enables the mode wherein the
output toggles between two
defined codes.
Inactive
25
00X
SINGLE_CUSTOM
_PAT
Enables the mode wherein the
output is a constant specified
code.
Inactive
XX
BITS_CUSTOM1
<9:8>
2MSBs for a single custom
pattern (and for the first code of
the dual custom pattern). <9> is
the MSB.
Inactive
XX
BITS_CUSTOM2 2MSBs for the second code of
<9:8>
the dual custom pattern.
Inactive
26
X
X
X
X
X
X XX
BITS_CUSTOM1
<7:0>
8 lower bits for the single custom
pattern (and for the first code of
the dual custom pattern). <0> is
the LSB.
Inactive
27
X
X
X
X
X
X XX
BITS_CUSTOM2 8 lower bits for the second code
<7:0>
of the dual custom pattern.
Inactive
X X X X GAIN_CH1<3:0> Programmable gain channel 1.
0dB gain
XXXX
GAIN_CH2<3:0> Programmable gain channel 2.
0dB gain
2A
X
X XX
GAIN_CH3<3:0> Programmable gain channel 3.
0dB gain
X
X
X
X
GAIN_CH4<3:0> Programmable gain channel 4.
0dB gain
X
X
X
X
GAIN_CH5<3:0> Programmable gain channel 5.
0dB gain
X
X XX
GAIN_CH6<3:0> Programmable gain channel 6.
0dB gain
2B
XXXX
GAIN_CH7<3:0> Programmable gain channel 7.
0dB gain
X X X X GAIN_CH8<3:0> Programmable gain channel 8.
0dB gain
(1) The unused bits in each register (identified as blank table cells) must be programmed as '0'.
(2) X = Register bit referenced by the corresponding name and description (default is 0).
(3) Bits marked as '0' should be forced to 0, and bits marked as '1' should be forced to 1 when the particular register is programmed.
(4) Multiple functions in a register should be programmed in a single write operation.
Copyright © 2008–2012, Texas Instruments Incorporated
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