TMS320F28335 Datasheet, PDF (147/195 Pages) Texas Instruments – Digital Signal Controllers (DSCs)

TMS320F28335, TMS320F28334, TMS320F28332
TMS320F28235, TMS320F28234, TMS320F28232
www.ti.com
SPRS439I – JUNE 2007 – REVISED MARCH 2011
6.13.2 SPI Slave Mode Timing
Table 6-34 lists the slave mode external timing (clock phase = 0) and Table 6-35 (clock phase = 1).
Figure 6-20 and Figure 6-21 show the timing waveforms.
Table 6-34. SPI Slave Mode External Timing (Clock Phase = 0)^{(1) (2) (3) (4) (5)}
NO.
MIN
MAX
12 t_c(SPC)S
13 t_w(SPCH)S
t_w(SPCL)S
14 t_w(SPCL)S
t_w(SPCH)S
15 t_{d(SPCH-SOMI)S}
t_{d(SPCL-SOMI)S}
16 t_{v(SPCL-SOMI)S}
Cycle time, SPICLK
Pulse duration, SPICLK high (clock polarity = 0)
Pulse duration, SPICLK low (clock polarity = 1)
Pulse duration, SPICLK low (clock polarity = 0)
Pulse duration, SPICLK high (clock polarity = 1)
Delay time, SPICLK high to SPISOMI valid (clock polarity = 0)
Delay time, SPICLK low to SPISOMI valid (clock polarity = 1)
Valid time, SPISOMI data valid after SPICLK low
(clock polarity = 0)
4t_c(LCO)
0.5t_c(SPC)S – 10
0.5t_c(SPC)S – 10
0.5t_c(SPC)S – 10
0.5t_c(SPC)S – 10
0.75t_c(SPC)S
0.5t_c(SPC)S
0.5t_c(SPC)S
0.5t_c(SPC)S
0.5t_c(SPC)S
35
35
t_{v(SPCH-SOMI)S}
Valid time, SPISOMI data valid after SPICLK high
(clock polarity = 1)
0.75t_c(SPC)S
19 t_{su(SIMO-SPCL)S}
t_{su(SIMO-SPCH)S}
20 t_{v(SPCL-SIMO)S}
Setup time, SPISIMO before SPICLK low (clock polarity = 0)
Setup time, SPISIMO before SPICLK high (clock polarity = 1)
Valid time, SPISIMO data valid after SPICLK low
(clock polarity = 0)
35
35
0.5t_c(SPC)S – 10
t_{v(SPCH-SIMO)S}
Valid time, SPISIMO data valid after SPICLK high
(clock polarity = 1)
0.5t_c(SPC)S – 10
(1) The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.
(2) t_c(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
(3) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX
Slave mode transmit 12.5-MHz MAX, slave mode receive 12.5-MHz MAX.
(4) t_c(LCO) = LSPCLK cycle time
(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
UNIT
ns
ns
ns
ns
ns
ns
ns
Copyright © 2007–2011, Texas Instruments Incorporated
Electrical Specifications 147
Submit Documentation Feedback
Product Folder Link(s): TMS320F28335 TMS320F28334 TMS320F28332 TMS320F28235 TMS320F28234
TMS320F28232