TMS320F28030 Datasheet, PDF (144/157 Pages) Texas Instruments – Piccolo Microcontrollers

TMS320F28030, TMS320F28031, TMS320F28032
TMS320F28033, TMS320F28034, TMS320F28035
SPRS584E – APRIL 2009 – REVISED MARCH 2011
www.ti.com
LOCATION
Section 4.2.1
Section 4.3
Figure 5-1
Section 6.3
Table 6-1
Table 6-5
Figure 6-14
Figure 6-15
Figure 6-16
Figure 6-20
Table 6-36
Table 6-40
Table 6-40
Table 6-41
Table 6-42
Table 6-42
ADDITIONS, DELETIONS, AND MODIFICATIONS
ADC:
• Added Section 4.2.1.1, Features
• "ADC Connections if the ADC is Not Used" section:
– NOTE: Changed "They should be grounded through a resistor" to "They should be grounded through a
1-kΩ resistor"
Serial Peripheral Interface (SPI) Module:
• First paragraph: Changed "One SPI module (SPI-A) is available" to "Up to two SPI modules are available"
Device Nomenclature:
• PACKAGE TYPE: Updated descriptions of 64-Pin PAG and 80-Pin PN
• Updated description of "Q" temperature range
Electrical Characteristics:
• Removed "V_DD BOR trip point" parameter
• Removed "V_DD over-voltage trip point" parameter
• VREG V_DD output:
– Removed MIN value of 1.865 V
– Removed MAX value of 1.955 V
• Updated footnote
TMS320F2803x Current Consumption at 60-MHz SYSCLKOUT:
• VREG ENABLED:
– IDLE: Added I_DDIO MAX of 23 mA
– STANDBY: Added I_DDIO MAX of 9 mA
Internal Zero-Pin Oscillator (INTOSC1/INTOSC2) Characteristics:
• Updated "In order to achieve better oscillator accuracy ..." footnote
• Added "Frequency range ensured only when VREG is enabled, VREGENZ = V_SS" footnote
IDLE Entry and Exit Timing:
• Added footnote about IDLE instruction and OSCCLK cycles
STANDBY Entry and Exit Timing Diagram:
• Added footnote about IDLE instruction and OSCCLK cycles
HALT Wake-Up Using GPIOn:
• Added footnote about IDLE instruction and OSCCLK cycles
SPI Master Mode External Timing (Clock Phase = 0):
• Replaced drawing
ADC Electrical Characteristics:
• Changed "V_REFLO is always connected to V_SSA" footnote to "V_REFLO is always connected to V_SSA on the
64-pin PAG device"
• Changed "V_REFHI must not exceed V_DDA when using either internal or external reference modes. Since V_REFHI
is tied to ADCINA0, the input signal on ADCINA0 must not exceed V_DDA" footnote to "V_REFHI must not exceed
V_DDA when using either internal or external reference modes. Since V_REFHI is tied to ADCINA0 on the 64-pin
PAG device, the input signal on ADCINA0 must not exceed V_DDA"
Changed title from "Flash Endurance for T Temperature Material" to "Flash/OTP Endurance for T Temperature
Material"
Flash/OTP Endurance for T Temperature Material:
• Added "ERASE/PROGRAM TEMPERATURE" column heading
• N_OTP [OTP endurance for the array (write cycles)]:
– Changed temperature range from "0°C to 105°C (ambient)" to "0°C to 30°C (ambient)"
Added "Flash/OTP Endurance for S Temperature Material" table
Changed title from "Flash Endurance for Q and S Temperature Material" to "Flash/OTP Endurance for Q
Temperature Material"
Flash/OTP Endurance for Q Temperature Material:
• Added "ERASE/PROGRAM TEMPERATURE" column heading
• N_OTP [OTP endurance for the array (write cycles)]:
– Changed temperature range from "–40°C to 125°C (ambient)" to "–40°C to 30°C (ambient)"
144 C-to-D Revision History
Copyright © 2009–2011, Texas Instruments Incorporated
Submit Documentation Feedback
focus.ti.com: TMS320F28030 TMS320F28031 TMS320F28032 TMS320F28033 TMS320F28034 TMS320F28035