TMS320C28346_11 Datasheet, PDF (143/170 Pages) Texas Instruments – Delfino Microcontrollers

TMS320C28346, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28342, TMS320C28341
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SPRS516B – MARCH 2009 – REVISED JULY 2010
Unless otherwise specified, all XINTF timing is applicable for the clock configurations shown in Table 6-36.
Table 6-36. XINTF Clock Configurations for SYSCLKOUT = 300 MHz
MODE
SYSCLKOUT
1
Example:
300 MHz
2
Example:
300 MHz
3
Example:
300 MHz
4
Example:
300 MHz
5
Example:
300 MHz
6
Example:
300 MHz
7
Example:
300 MHz
8
Example:
300 MHz
(1) The XCLKOUT signal is limited to a maximum frequency of 75 MHz.
XTIMCLK
SYSCLKOUT
300 MHz
SYSCLKOUT
300 MHz
SYSCLKOUT
300 MHz
SYSCLKOUT
300 MHz
1/2 SYSCLKOUT
150 MHz
1/2 SYSCLKOUT
150 MHz
1/2 SYSCLKOUT
150 MHz
1/2 SYSCLKOUT
150 MHz
The relationship between SYSCLKOUT and XTIMCLK is shown in Figure 6-21.
XCLKOUT ⁽¹⁾
SYSCLKOUT
300 MHz
1/2 SYSCLKOUT
150 MHz
1/2 SYSCLKOUT
150 MHz
1/4 SYSCLKOUT
75 MHz
1/2 SYSCLKOUT
150 MHz
1/4 SYSCLKOUT
75 MHz
1/4 SYSCLKOUT
75 MHz
1/8 SYSCLKOUT
37.5 MHz
PCLKR3[XINTFENCLK]
00
1
XTIMING0
XTIMING6 ^{LEAD/ACTIVE/TRAIL}
XTIMING7
XBANK
C28x ^SYSCLKOUT _{/2 1}
CPU
0
XTIMCLK
XINTCNF2 (XTIMCLK)
/2 1
0
/2 1
0
XINTCNF2
XINTCNF2
(CLKMODE) _(BY4CLKMODE)
XCLKOUT
XINTCNF2
(CLKOFF)
Figure 6-21. Relationship Between XTIMCLK and SYSCLKOUT
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Electrical Specifications 143
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