TPS54377_15 Datasheet, PDF (14/23 Pages) Texas Instruments – 1.6 MHz, 3-V TO 6-V INPUT, 3-A SYNCHRONOUS STEP-DOWN SWIFT™ CONVERTER WITH DISABLED SINKING DURING START-UP

TPS54377
SLVS779 – SEPTEMBER 2007
low-side FET remains on until the VSENSE voltage
decreases to a range that allows the PWM
comparator to change states. The TPS54377 is
capable of sinking current continuously until the C_O
reaches the regulation set-point.
If the current limit comparator trips for longer than
100 ns, the PWM latch resets before the PWM ramp
exceeds the error amplifier output. The high-side FET
turns off and low-side FET turns on to decrease the
energy in the output inductor, and consequently, the
output current. This process is repeated each cycle in
which the current limit comparator is tripped.
Dead-Time Control and MOSFET Drivers
Adaptive dead-time control prevents shoot-through
current from flowing in both N-channel power
MOSFETs during the switching transitions by actively
controlling the turn-on times of the MOSFET drivers.
The high-side driver does not turn on until the gate
drive voltage to the low-side FET is below 2 V. The
low-side driver does not turn on until the voltage at
the gate of the high-side MOSFETs is below 2 V. The
high-side and low-side drivers are designed with a
300-mA source and sink capability to drive the power
MOSFETs gates. The low-side driver is supplied from
VIN, while the high-side drive is supplied from the
BOOT pin. A bootstrap circuit uses an external BOOT
capacitor and an internal 2.5-Ω bootstrap switch
connected between the VIN and BOOT pins. The
integrated bootstrap switch improves drive efficiency
and reduces external component count.
Overcurrent Protection
The cycle by cycle current limiting is achieved by
sensing the current flowing through the high-side
MOSFET and differential amplifier, and comparing it
to the preset overcurrent threshold. The high-side
MOSFET is turned off within 200 ns of reaching the
current limit threshold. A 100-ns leading edge
blanking circuit prevents false tripping of the current
limit. Current limit detection occurs only when current
flows from VIN to PH when sourcing current to the
output filter. Load protection during current sink
operation is provided by thermal shutdown.
Thermal Shutdown
The device uses the thermal shutdown to turn off the
power MOSFETs and disable the controller if the
junction temperature exceeds 150°C. The device is
released from shutdown when the junction
temperature decreases to 10°C below the thermal
shutdown trip point and starts up under control of the
slow-start circuit. Thermal shutdown provides
protection when an overload condition is sustained for
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several milliseconds. With a persistent fault condition,
the device cycles continuously; starting up by control
of the soft-start circuit, heating up due to the fault,
and then shutting down upon reaching the thermal
shutdown point.
Power Good (PWRGD)
The power good circuit monitors for undervoltage
conditions on VSENSE. If the voltage on VSENSE is
10% below the reference voltage, the open-drain
PWRGD output is pulled low. PWRGD is also pulled
low if VIN is less than the UVLO threshold, or
SS/ENA is low, or thermal shutdown is asserted.
When VIN = UVLO threshold, SS/ENA = enable
threshold, and VSENSE > 90% of V_ref, the open drain
output of the PWRGD pin is high. A hysteresis
voltage equal to 3% of V_ref and a 35-μs falling edge
deglitch circuit prevent tripping of the power good
comparator due to high frequency noise.
OUTPUT VOLTAGE LIMITATIONS
Due to the internal design of the TPS54377, there are
both upper and lower output voltage limits for any
given input voltage. Additionally, the lower boundary
of the output voltage set point range is also
dependent on operating frequency. The upper limit of
the output voltage set point is constrained by the
maximum duty cycle of 90% and is given by
Equation 5:
V_Omax = 0.9 x V_Imin - I_Omax [ (-0.016 x V_Imin + 0.184) + RL]
(5)
Where:
V_Imin = minimum input voltage
I_Omax = maximum load current
RL = series resistance of the output inductor
Equation 5 assumes maximum on resistance for the
internal high-side and low-side FETs.
The lower limit is constrained by the minimum
controllable on time which may be as high as 150 ns.
The approximate minimum output voltage for a given
input voltage, operating frequency, and minimum load
current is given in Equation 6:
V_Omin = (150E-9 x V_Imax x Fs x 1.08) - I_omin x
[ ( ) ] -0.026
3
X V_imax + 0.111 + RL
(6)
Where:
V_I = maximum input voltage
Fs = programmed operating frequency
I_O = minimum load current
RL = series resistance of the output inductor
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