TPS5430-Q1_15 Datasheet, PDF (14/33 Pages) Texas Instruments – TPS5430-Q1 3-A Wide-Input-Range Step-Down Converter

TPS5430-Q1
SLVS751D – NOVEMBER 2007 – REVISED JULY 2015
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ICOUT(RMS)
+
1
Ǹ₁₂
ȡ ^{ǒ Ǔ} ȣ ^{VOUT VIN(MAX) * VOUT}
ȧȢ ȧȤ _{VIN(MAX) LOUT FSW NC}
(10)
Where:
N_C is the number of output capacitors in parallel.
F_SW is the switching frequency.
Other capacitor types can be used with the TPS5430-Q1, depending on the needs of the application.
The maximum ESR of the output capacitor also determines the amount of output ripple as specified in the initial
design parameters. The output ripple voltage is the inductor ripple current times the ESR of the output filter.
Check that the maximum specified ESR as listed in the capacitor data sheet results in an acceptable output
ripple voltage:
( ) ^ESR_MAX ^{× V}_OUT ^{× V}_IN(MAX) ^{– V}_OUT
V_PP (MAX) =
N_C × V_IN(MAX) × L_OUT × F_SW
(11)
Where:
ΔV_PP is the desired peak-to-peak output ripple.
N_C is the number of parallel output capacitors.
F_SW is the switching frequency.
For this design example, a single 220-μF output capacitor is chosen for C3. The calculated RMS ripple current is
143 mA and the maximum ESR required is 40 mΩ. A capacitor that meets these requirements is a Sanyo
Poscap 10TPB220M, rated at 10 V with a maximum ESR of 40 mΩ and a ripple current rating of 3 A. An
additional small 0.1-μF ceramic bypass capacitor may also used, but is not included in this design.
The minimum ESR of the output capacitor should also be considered. For good phase margin, the ESR zero
when the ESR is at a minimum should not be too far above the internal compensation poles at 24 kHz and
54 kHz.
8.2.1.2.4 Output Voltage Setpoint
The output voltage of the TPS5430-Q1 is set by a resistor divider (R1 and R2) from the output to the VSENSE
pin. Calculate the R2 resistor value for the output voltage of 5 V using Equation 12:
R2
+
R1
VOUT
1.221
* 1.221
(12)
For any TPS5430-Q1 design, start with an R1 value of 10 kΩ. R2 is then 3.24 kΩ for 5-V output.
8.2.1.2.5 Boot Capacitor
The boot capacitor should be 0.01 μF.
8.2.1.2.6 Catch Diode
The TPS5430-Q1 is designed to operate using an external catch diode between PH and GND. The selected
diode must meet the absolute maximum ratings for the application: reverse voltage must be higher than the
maximum voltage at the PH pin, which is V_IN(MAX) + 0.5 V. Peak current must be greater than I_OUT(MAX) plus one-
half the peak to peak inductor current. Forward voltage drop should be small for higher efficiencies. It is
important to note that the catch diode conduction time is typically longer than the high-side FET on time, so
attention paid to diode parameters can make a marked improvement in overall efficiency. Additionally, check that
the device chosen is capable of dissipating the power losses. For this design, a Diodes, Inc. B340A is chosen,
with a reverse voltage of 40 V, forward current of 3 A, and forward voltage drop of 0.5 V.
14
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