TPS51120 Datasheet, PDF (14/34 Pages) Texas Instruments – DUAL CURRENT MODE, SYNCHRONOUS STEP-DOWN CONTROLLER WITH 100-mA STANDBY REGULATORS FOR NOTEBOOK SYSTEM POWER

TPS51120
SLUS670A – JULY 2005 – REVISED AUGUST 2005
www.ti.com
DETAILED DESCRIPTION (continued)
2V, 50 µA Sink/Source Reference (VREF2)
This is a handy reference for generating auxiliary voltages. The tolerance is ±2% over 50-µA load and 0°C to
85°C ambient temperature ranges. The four-state logic (SKIPSEL, TONSEL) takes advantage of this reference
for additional selection modes. This reference is enabled when both EN3 and EN5 become high, shuts down
after both switchers are turned off and VREG5 or VREG3 is shut down. Please refer to Table 4. If this output is
forcibly tied down to ground, both SMPS are turned off without latch. Bypass VREF2 pin to GND by a 1-nF
capacitor.
Low-Side Driver
The low-side gate driver, DRVL, is designed to drive high current low R_DS(on) N-channel MOSFET(s). The
maximum drive voltage is 5.5 V which is delivered from VREF5 pin. The instantaneous drive current is supplied
from the output capacitor at the VREF5 pin. The average drive current is equal to the FET’s gate charge at
VGS=5 V times switching frequency. The VREG5 pin voltage may contain high frequency noise due to parasitic
inductance by wiring and pointing current flow into the gate capacitor. The drive capability is represented by its
internal resistance, which are 3.5 Ω for VREG5 to DRVL and 1.5 Ω for DRVL to PGND. Adaptive dead time
control generates delay times between top MOSFET off to bottom MOSFET on, and bottom MOSFET off to top
MOSFET on, preventing the totem-pole switches to shoot through. Top MOSFET off is detected as LL-node
voltage declining below 2 V. Bottom MOSFET off is detected as DRVL voltage become 1.1 V.
High-Side Driver
The high-side gate driver, DRVH, is designed to drive high current, low R_DS(on) N-channel MOSFET(s). When
configured as a LL-node referenced floating driver, connect 0.1-µF ceramic capacitor between corresponding
VBST pin and LL pin. A 5-V bias voltage is delivered from VREG5 supply. VBST is internally connected to
VREG5 through a high voltage PN diode. This internal diode provides sufficient gate voltage for ordinary 4.5-V
drive power MOSFETs and helps reducing external component. However, in the case where the gate bias
voltage is critical for driving the top MOSFET, application designer may add an external schottky diode from
VREG5 pin to VBST pin. Note schottky diodes have quite high reverse leakage current at high temperature. The
instantaneous drive current is supplied by the flying capacitor connected between VBST and LL pins. The
average drive current is equal to the gate charge at VGS=5 V times switching frequency. The drive capability is
represented by its internal resistance, which are 3.5-Ω for VBST to DRVH and 1.5Ω for DRVH to LL. The
maximum recommended voltage that can be applied between DRVH pin and LL pin is 5.5 V, DRVH pin to PGND
pin is 34 V.
Soft-Start
The TPS51120 has an internal 3-ms voltage-servo soft start for each channel. When the EN1 or EN2 pin
exceeds 0.9 V, an internal DAC begins ramping up the reference voltage. Smooth control of the output voltage
during start up is maintained. However, if a slower soft-start is required, an external capacitor may be tied from
the EN1 or EN2 pin to GND. In this case, the TPS51120 charges the external capacitor with the integrated 2-µA
current source. The lower of either the EN voltage slew rate or the internal soft start slew rate dominates the
start-up ramp. In addition, if tracking discharge is required, the EN pin can be used to control the output voltage
discharge smoothly. An approximate value for the soft start reference voltage as a function of EN voltage is
V_SSREF = (V_ENX– 0.9)/1.5 < 1 V. At the beginning of soft-start period, the rectifying MOSFET maintains an off
state until the top MOSFET is turned on for at least once. This prevents high negative current to flow back from
the output capacitor in the event of output capacitor pre-charged condition.
Soft-Stop
Discharge mode or ‘Soft Stop’ is always on during Faults or Disable. In this mode, an event that would cause the
switcher to be turned off (EN1 or EN2 low, OVP, UVP, UVLO) causes the output to be discharged through 10-Ω
transistor inside the VO terminal. The external rectifying MOSFET is not turned on for the soft off operation to
avoid a chance to cause negative voltage at the output. Soft-stop time constant is a function of the output
capacitance and the resistance of the discharge transistor. This discharge ensures that, upon restart, the
regulated voltage always starts from zero volts. In case a SMPS is restarted before discharge completion,
soft-stop is terminated and the switching resumes after the reference level comes back to the remaining output
voltage.
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