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| SN65LVDS305 Datasheet, PDF (14/25 Pages) Texas Instruments – PROGRAMMABLE 27-BIT DISPLAY SERIAL INTERFACE TRANSMITTER | |||
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SN65LVDS305
SLLS744 â AUGUST 2006
PARAMETER MEASUREMENT INFORMATION (continued)
www.ti.com
CLK+, Dx+
CLKâ, Dxâ
SN65LVDS305
C1 = 1 pF
R1 = 49.9 W
VOD
R2 = 49.9 W
VDx+ or VCLK+
VDxâ or VCLKâ
VOCM
VOCM
C2 = 1 pF
C3 = 1 pF
975 mV (Nom)
825 mV (Nom)
VOCM (pp)
VOCM (ss)
NOTES:
A. 15-MHz output test pattern on all differential outputs (CLK and D):
this is achieved by: 1. fPCLK = 15 MHz
2. Inputs R[7:0] connected to VDD, all other data inputs set to GND.
B. C1, C2, and C3 include instrumentation and fixture capacitance, tolerance ±20%; C, R1, and R2 tolerance ±1%
C. The measurement of VOCM (pp) and VOC(ss) are taken with test equipment bandwidth >1 GHz.
Figure 8. Driver Output Voltage Test Circuit and Definitions
CMOS
Data In
R7(nâ1)
R6(nâ1)
PCLK
CLKâ
CLK+
D+
pixel (n)
R7(n)
R6(n)
tPROP
pixel (n+1)
R7(n+1)
R6(n+1)
VDD /2
pixel (nâ2)
CP R7 R6
R7(nâ1) R6(nâ1)
pixel (nâ1)
Figure 9. tpd(L) Propagation Delay Input to Output (CPOL = 0)
1
Noise
1
Generator
100 mV
2
10 mF
SN65LVDS305
V DDPLLA
VDDPLLD
V DD
VDDLVDS
GND
Note: The generator regulates the
noise amplitude at point 1 to the
target amplitude given under the table
Recommended Operating Conditions
1.8-V
supply
Figure 10. Power Supply Noise Test Setup
CP R7 R6
R7(n) R6(n)
14
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