LP38798 Datasheet, PDF (14/23 Pages) Texas Instruments – LP38798-ADJ High PSRR, Ultra Low Noise, 800 mA Linear Voltage Regulator for RF/Analog Circuits

LP38798
SNOSCT6A – MARCH 2013 – REVISED MAY 2013
www.ti.com
OUTPUT CAPACITOR: The LP38798 requires an output capacitance of at least 1 µF, ceramic or tantalum,
however a minimum output capacitance of 10 µF is strongly recommended if fast load transient conditions are
expected. While the LP38798 is designed to work with Ceramic output capacitors, the output capacitor can be
Ceramic, Tantalum, or a combination. The total output capacitance should be sized appropriately to handle any
fast load current steps. Capacitance type, tolerance, ESR, as well as temperature and voltage characteristics,
must be considered when selecting an output capacitor for the application.
Even though the LP38798 is stable with an output capacitance of 1 µF to 10 µF, a single output capacitor will
generally not be able to provide the best PSRR performance across a wide frequency range. Multiple parallel
capacitors, each with a different self-resonance frequency will provide better performance over a wider frequency
range.
The output capacitor must be located not more than 0.5" from the output pin and returned to a clean analog
ground to the LP38798 GND pin.
Charge Pump
The charge pump is running when both the input voltage is above the UVLO threshold (2.65 V typical) and the
EN pin voltage is above the V_EN(ON) threshold (1.24 V typical). The typical charge pump operating frequency is
3.5 MHz.
A low leakage 10 nF X7R storage capacitor is required between the CP pin and ground to store the energy
required for gate drive of the internal NMOS pass device.
Do not make any other connection to the CP pin. Loading this pin in any manner will degrade regulator
performance. No external biasing may be applied to, or derived from, this pin, as permanent damage to the
internal charge pump circuitry may occur.
Programming the Output Voltage
Current sourced from the SET pin, through R1 and R2, must be kept to less than 100 µA. The minimum allowed
value for R2 is 12.9 kΩ;
I_SET = V_FB / R2
(1)
R2_MIN = V_FB(MAX) / 100 μA
(2)
R2_MIN = 12.9 kΩ;
(3)
The values for R1 and R2 may be adjusted as needed to achieve the desired output voltage as long as the value
for R2 is no less than 12.9 kΩ. The maximum recommended value for R2 is 100 kΩ.
The following equation is used to determine the output voltage:
V_OUT = ( V_FB x ( 1 + ( R1 / R2 ) ) ) + V_OS
(4)
Alternately, the following formula can be used to determine the appropriate R1 value for a given R2 value:
R1 = R2 x ( ( (V_OUT) / V_FB) – 1)
(5)
The following table suggests some ±1% values for R1 and R2 for a range of output voltages using the typical V_FB
value of 1.200V. This is not a definitive list, as other combinations exist that will provide similar, possibly better,
performance.
Target V_OUT
1.5 V
1.8 V
2.0 V
2.5 V
3.0 V
3.3 V
5.0 V
R1
4.22 kΩ
10.5 kΩ
10.0 kΩ
16.2 kΩ
21.0 kΩ
23.2 kΩ
47.5 kΩ
R2
16.9 kΩ
21.0 kΩ
15.0 kΩ
15.0 kΩ
14.0 kΩ
13.3 kΩ
15.0 kΩ
Typical V_OUT
1.5 V
1.8 V
2.0 V
2.496 V
3.0 V
3.293 V
5.0 V
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