LDC1000-Q1_15 Datasheet, PDF (14/40 Pages) Texas Instruments – LDC1000-Q1 Inductance to Digital Converter

LDC1000-Q1
SLOS886B – SEPTEMBER 2014 – REVISED OCTOBER 2014
Device Functional Modes (continued)
INTB
tODRt
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CSB
SPI
CMD:
Read 0x21
Data
Read
t
Figure 15. Behavior of the INTB Pin in DRDYB Mode
7.5 Programming
7.5.1 Digital Interface
The LDC1000-Q1 device uses a 4-wire SPI interface to access control and data registers. The LDC1000-Q1
device is an SPI slave device and does not initiate any transactions.
7.5.1.1 SPI Description
A typical serial interface transaction begins with an 8-bit instruction that is comprised of a read-write (R/W) bit
(MSB, R = 1) and a 7-bit address of the register followed by a data field that is typically 8 bits. However, the data
field can be extended to a multiple of 8 bits by providing sufficient SPI clocks. See the Extended SPI
Transactions section.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
SCLK
t_IAG
CSB
SDI
SDO
tCOMMAND FIELDt
tDATA FIELDt
C7 C6 C5 C4 C3 C2 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0
(MSB)
(LSB)
R/Wb A6 A5 A4 A3 A2 A1 A0
Write DATA
R/Wb = Read/Write
0: Write Data
1: Read Data
Address (7-bits)
High-Z
D7 D6 D5 D4 D3 D2 D1 D0
(MSB)
(LSB)
Read DATA
tSingle Access Cyclet
Data (8-bits)
Figure 16. Serial Interface Protocol
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