DAC7551 Datasheet, PDF (14/18 Pages) Texas Instruments – 12-BIT, ULTRALOW GLITCH, VOLTAGE OUTPUT DIGITAL-TO-ANALOG CONVERTER

DAC7551
SLAS441 – MARCH 2005
THEORY OF OPERATION
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D/A SECTION
The architecture of the DAC7551 consists of a string
DAC followed by an output buffer amplifier. Figure 26
shows a generalized block diagram of the DAC
architecture.
DAC Register
V_REFH
_
Ref +
Resistor String +
Ref −
V_FB
V_OUT
V_REFL
Figure 26. Typical DAC Architecture
The input coding to the DAC7551 is unsigned binary,
which gives the ideal output voltage as:
V_OUT = 2 x V_REFL + (V_REFH – V_REFL) x D/4096
Where D = decimal equivalent of the binary code that
is loaded to the DAC register which can range from 0
to 4095.
V_REFH
To Output
Amplifier
R
R
R
R
V_REFL
Figure 27. Typical Resistor String
RESISTOR STRING
The resistor string section is shown in Figure 27. It is
simply a string of resistors, each of value R. The
digital code loaded to the DAC register determines at
which node on the string the voltage is tapped off to
be fed into the output amplifier. The voltage is tapped
off by closing one of the switches connecting the
string to the amplifier. Because it is a string of
resistors, it is specified monotonic.
OUTPUT BUFFER AMPLIFIERS
The output buffer amplifier is capable of generating
rail-to-rail voltages on its output, which gives an
output range of 0 V to V_DD. It is capable of driving a
load of 2 kΩ in parallel with up to 1000 pF to GND.
The source and sink capabilities of the output ampli-
fier can be seen in the typical curves. The slew rate is
1 V/µs with a half-scale settling time of 3 µs with the
output unloaded.
DAC External Reference Input
There is a single reference input pin for the DAC. The
reference input is unbuffered. The user can have a
reference voltage as low as 0.25 V and as high as
V_DD because there is no restriction due to headroom
and footroom of any reference amplifier.
It is recommended to use a buffered reference in the
external circuit (e.g., REF3140). The input impedance
is typically 100 kΩ.
Power-On Reset
On power up, the internal register is cleared and the
DAC channel is updated with zero-scale voltage. The
DAC output remains in this state until valid data is
written. This is particularly useful in applications
where it is important to know the state of the DAC
output while the device is powering up. In order not to
turn on ESD protection devices, V_DD should be
applied before any other pin is brought high.
Power Down
The DAC7551 has a flexible power-down capability.
During a power-down condition, the user has flexi-
bility to select the output impedance of the DAC.
During power-down operation, the DAC can have
either 1-kΩ, 100-kΩ, or Hi-Z output impedance to
ground.
Asynchronous Clear
The DAC7551 output is asynchronously set to
zero-scale voltage immediately after the CLR pin is
brought low. The CLR signal resets all internal
registers and therefore behaves like the Power-On
Reset. The DAC7551 updates at the first rising edge
of the SYNC signal that occurs after the CLR pin is
brought back to high.
SERIAL INTERFACE
The DAC7551 is controlled over a versatile 3-wire
serial interface, which operates at clock rates up to
50 MHz and is compatible with SPI, QSPI, Microwire,
and DSP interface standards.
In order to initialize the serial interface for the next
update, the DAC7551 requires a falling SCLK edge
after the rising SYNC.
16-Bit Word and Input Shift Register
The input shift register is 16 bits wide. DAC data is
loaded into the device as a 16-bit word under the
control of a serial clock input, SCLK, as shown in the
Figure 1 timing diagram. The 16-bit word, illustrated
in Table 1, consists of four control bits followed by 12
bits of DAC data. The data format is straight binary
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