ADS8345 Datasheet, PDF (14/20 Pages) Texas Instruments – 16-Bit, 8-Channel Serial Output Sampling ANALOG-TO-DIGITAL CONVERTER

Since one clock cycle of the serial clock is consumed with
BUSY going HIGH (while the MSB decision is being made),
16 additional clocks must be given to clock out all 16 bits of
data; thus, one conversion takes a minimum of 25 clock
cycles to fully read the data. Since most microprocessors
communicate in 8-bit transfers, this means that an additional
transfer must be made to capture the LSB.
There are two ways of handling this requirement. One is
where the beginning of the next control byte appears at the
same time the LSB is being clocked out of the ADS8345 (see
Figure 6). This method allows for maximum throughput and
24 clock cycles per conversion.
The other method is shown in Figure 8, which uses 32 clock
cycles per conversion; the last seven clock cycles simply
shift out zeros on the D_OUT line. BUSY and D_OUT go into a
high-impedance state when CS goes HIGH; after the next
CS falling edge, BUSY will go LOW.
Internal Clock Mode
In internal clock mode, the ADS8345 generates its own
conversion clock internally. This relieves the microprocessor
from having to generate the SAR conversion clock and
allows the conversion result to be read back at the processor’s
convenience, at any clock rate from 0MHz to 2.0MHz. BUSY
goes LOW at the start of a conversion and then returns HIGH
when the conversion is complete. During the conversion,
BUSY will remain LOW for a maximum of 8µs. Also, during
the conversion, DCLK should remain LOW to achieve the
best noise performance. The conversion result is stored in an
internal register; the data may be clocked out of this register
any time after the conversion is complete.
If CS is LOW when BUSY goes LOW following a conversion,
the next falling edge of the external serial clock will write out
the MSB on the D_OUT line. The remaining bits (D14-D0) will
be clocked out on each successive clock cycle following the
MSB. If CS is HIGH when BUSY goes LOW then the D_OUT
line will remain in tri-state until CS goes LOW, as shown in
Figure 9. CS does not need to remain LOW once a conver-
sion has started. Note that BUSY is not tri-stated when CS
goes HIGH in internal clock mode.
Data can be shifted in and out of the ADS8345 at clock rates
exceeding 2.4MHz, provided that the minimum acquisition
time t_ACQ, is kept above 1.7µs.
Digital Timing
Figure 7 and Tables VI and VII provide detailed timing for the
digital interface of the ADS8345.
SYMBOL
DESCRIPTION
MIN TYP MAX UNITS
t_ACQ
Acquisition Time
1.5
t_DS
D_IN Valid Prior to DCLK Rising 100
t_DH
D_IN Hold After DCLK HIGH
10
t_DO
DCLK Falling to D_OUT Valid
t_DV
CS Falling to D_OUT Enabled
t_TR
CS Rising to D_OUT Disabled
t_CSS
CS Falling to First DCLK Rising 100
t_CSH
CS Rising to DCLK Ignored
0
t_CH
DCLK HIGH
200
t_CL
DCLK LOW
200
t_BD
DCLK Falling to BUSY Rising
t_BDV
CS Falling to BUSY Enabled
t_BTR
CS Rising to BUSY Disabled
µs
ns
ns
200
ns
200
ns
200
ns
ns
ns
ns
ns
200
ns
200
ns
200
ns
TABLE VI. Timing Specifications (+V_CC = +2.7V to 3.6V,
T_A = –40°C to +85°C, C_LOAD = 50pF).
CS
DCLK
D_IN
BUSY
1
Idle
S A2 A1 A0
(START)
t_ACQ
8
1
Acquire
SGL/
DIF
PD1
PD0
8
1
Conversion
8
1
D_OUT
15 14 13 12 11 10 9 8
(MSB)
7654321
0
(LSB)
FIGURE 8. External Clock Mode, 32 Clocks Per Conversion.
8
Idle
Zero Filled...
CS
DCLK
D_IN
BUSY
D_OUT
1
Idle
S A2 A1 A0
(START)
t_ACQ
8
Acquire
SGL/
DIF
PD1
PD0
Conversion
FIGURE 9. Internal Clock Mode Timing.
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
15 14 13 12 11 10 9 8
(MSB)
7654321
0
(LSB)
Zero Filled...
14
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