ADS7863_08 Datasheet, PDF (14/40 Pages) Texas Instruments – Dual, 2MSPS, 12-Bit, 2 + 2 or 3 + 3 Channel, Simultaneous Sampling ANALOG-TO-DIGITAL CONVERTER

ADS7863
SBAS383B – JUNE 2007 – REVISED MARCH 2008
APPLICATIONS INFORMATION
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GENERAL DESCRIPTION
The ADS7863 includes two 12-bit analog-to-digital
converters (ADCs) that operate based on the
successive-approximation register (SAR) principle.
The ADCs sample and convert simultaneously.
Conversion time can be as low as 406.25ns. Adding
the acquisition time of 62.5ns and an additional clock
cycle for setup/hold time requirements and skew
results in a maximum conversion rate of 2MSPS.
Each ADC has a fully differential, 2:1 multiplexer
front-end. In many common applications, all negative
input signals remain at the same constant voltage (for
example, 2.5V). In this type of application, the
multiplexer can be used in a pseudo-differential 3:1
mode, where CHx0– functions as a common-mode
input and the remaining three inputs (CHx0+, CHx1–,
and CHx1+) operate as separate inputs referred to
the common-mode input.
The ADS7863 also includes a 2.5V internal reference.
The reference drives a 10-bit digital-to-analog
converter (DAC), allowing the voltage at the REF_OUT
pin to be adjusted via the serial interface in 2.44mV
steps. A low-noise operational amplifier with unity
gain buffers the DAC output voltage and drives the
REF_OUT pin.
The ADS7863 offers a serial interface that is
compatible with the ADS7861. However, instead of
the A0 pin of the ADS7861 that controls the channel
selection, the ADS7863 offers a serial data input
(SDI) pin that supports additional functions described
in the Digital section of this data sheet (see also the
ADS7861 Compatibility section).
ANALOG
This section addresses the analog input circuit, the
ADCs, and the reference design of the device.
Analog Inputs
Each ADC is fed by an input multiplexer; see
Figure 31. Each multiplexer is either used in a
fully-differential 2:1 configuration (as described in
Table 1) or a pseudo-differential 3:1 configuration (as
shown in Table 2). The channel selection is
performed using bits C1 and C0 in the SDI register
(see also the Serial Data Input section).
CHx1+
CHx1-
CHx0+
CHx0-
Input
MUX
ADC+
ADC-
Figure 31. Input Multiplexer Configuration
The input path for the converter is fully differential
and provides a common-mode rejection of 72dB at
100kHz. The high CMRR also helps suppress noise
in harsh industrial environments.
Table 1. Fully Differential 2:1 Multiplexer
Configuration
C1
C0
ADC+
ADC–
0
0
CHx0+
CHx0–
1
1
CHx1+
CHx1–
Table 2. Pseudo-Differential 3:1 Multiplexer
Configuration
C1
C0
ADC+
ADC–
0
0
CHx0+
CHx0–
0
1
CHx1–
CHx0–
1
0
CHx1+
CHx0–
Each of the 2pF sample-and-hold capacitors (shown
as C_S in the Equivalent Input Circuit) is connected via
switches to the multiplexer output. Opening the
switches holds the sampled data during the
conversion process. After finishing the conversion,
both capacitors are pre-charged for the duration of
one clock cycle to the voltage present at the REF_IN
pin. After the pre-charging, the multiplexer outputs
are connected to the sampling capacitors again. The
voltage at the analog input pin is usually different
from the reference voltage; therefore, the sample
capacitors must be charged to within one-half LSB for
12-bit accuracy during the acquisition time t_ACQ (see
the Timing Characteristics).
Acquisition time is indicated with the BUSY signal
being held low. It starts by closing the input switches
(after finishing the previous conversion and
pre-charging) and finishes with the rising edge of the
CONVST signal. If the ADS7863 operates at full
speed, the acquisition time is typically 62.5ns.
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