ADS61JB23 Datasheet, PDF (14/45 Pages) Texas Instruments – 12-Bit Input-Buffered 80 MSPS ADC with JESD204A Output Interface

ADS61JB23
SLOS755 – DECEMBER 2012
www.ti.com
Table 7. Pins 24 and 28 - SDATA_TEST0 and SDOUT_TEST1 (in Parallel Interface Mode)
TEST1
0
0
1
1
TEST0
0
1
0
1
MODE
Normal mode. Input to JESD204A encoder is ADC data
Input to JESD204A encoder is B5B5. Output is a stream of D21.5 (alternating 1 and 0)
Input to JESD204A encoder is FF00
Input to JESD204A encoder is a pseudo random pattern 1+ X¹⁴ + X¹⁵ (irrespective of whether scrambler
is enabled or not)
SERIAL INTERFACE
The ADC has a set of internal registers, which can be accessed by the serial interface formed by pins Serial
interface Enable (SEN), Serial Interface Clock (SCLK) and Serial Interface Data (SDATA).
Serial shift of bits into the device is enabled when SEN is low. Serial data SDATA is latched at every falling edge
of SCLK when SEN is active (low). The serial data is loaded into the register at every 16^th SCLK falling edge
when SEN is low. In case the word length exceeds a multiple of 16 bits, the excess bits are ignored. Data can be
loaded in multiple of 16-bit words within a single active SEN pulse.
The first 8 bits form the register address and the remaining 8 bits are the register data. The interface can work
with SCLK frequency from 20 MHz down to very low speeds (few Hertz) and also with non-50% SCLK duty
cycle.
REGISTER INITIALIZATION
After power-up, the internal registers MUST be initialized to their default values. This can be done in one of two
ways:
1. Either through hardware reset by applying a high-going pulse on RESET pin (of width greater than 10ns) as
shown in Figure 8
OR
2. By applying software reset. Using the serial interface, set the S_RESET bit (D1 in register 0x00) to HIGH.
This initializes internal registers to their default values and then self-resets the S_RESET bit to LOW. In this
case the RESET pin is kept LOW.
Register Address
Register Data
SDATA
SCLK
A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
t_SCLK
t_DH
t_DSU
SEN
t_SLOADS
t_SLOADH
RESET
Figure 8. Serial Interface Timing
T0109-04
14
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