TPS65950 Datasheet, PDF (132/166 Pages) Texas Instruments – Integrated Power Management/Audio Codec Silicon Revision 1.0

TPS65950
Integrated Power Management/Audio Codec
SWCS032A – OCTOBER 2008 – REVISED DECEMBER 2008
12.2 Input Clock Specifications
The clock system accepts two input clock sources:
• 32-kHz crystal oscillator clock or sinusoidal/squared clock
• HFCLKIN high-frequency input clock
12.2.1 Clock Source Requirements
Table 12-1 lists the input clock requirements.
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Pad
32KXIN
32KXOUT
HFCLKIN
Table 12-1. TPS65950 Input Clock Source Requirements
Clock Frequency
Crystal
32.768 kHz
Square wave
Sine wave
19.2, 26, 38.4 MHz
Square wave
Sine wave
Stability
±30 ppm
–
–
±150 ppm
–
Duty Cycle
40%/60%
45%/55%
–
45%/55%
–
12.2.2 High-Frequency Input Clock
HFCLKIN is the high-frequency input clock. It can be a square- or sine-wave input clock. If a square-wave
input clock is provided, it is recommended to switch the block to bypass mode when possible to avoid
loading the clock.
Figure 12-2 shows the HFCLKIN clock distribution.
HFCLKIN Slicer
Slicer bypass
Clock
generator
SLICER_OK
HFCLKOUT
CLKEN2
CLKEN
Timer
Main state-machine
CLKREQ
SLEEP1
SLEEP2
Optional request
configurable by software
only for legacy support
Figure 12-2. HFCLKIN Clock Distribution
032-063
When a device needs a clock signal other than 32.768 kHz, it makes a clock request and activates the
CLKREQ pin. As a result, the TPS65950 immediately sets CLKEN to 1 to warn the clock provider in the
132 Clock Specifications
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