TPS54350 Datasheet, PDF(13/27 Page) Texas Instruments – 4.5-V 20-V INPUT, 3-A OUTPUT SYNCHRONOUS PWM SWITCHER WITH INTEGRATED FET(SWIFT)

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TPS54350 Datasheet, PDF (13/27 Pages) Texas Instruments – 4.5-V 20-V INPUT, 3-A OUTPUT SYNCHRONOUS PWM SWITCHER WITH INTEGRATED FET(SWIFT)

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TPS54350

SLVS456C â OCTOBER 2003 â REVISED OCTOBER 2004

APPLICATION INFORMATION

VIN

GND

VIN

UVLO

PWRGD

SYNC

ENA

COMP

BOOT

LSG

VBIAS

PGND

AGND

VSENSE

VOUT

GND

VIA to Ground Plane

Figure 21. TPS54350 PCB Layout

PCB LAYOUT

The VIN pins should be connected together on the printed

circuit board (PCB) and bypassed with a low ESR ceramic

bypass capacitor. Care should be taken to minimize the

loop area formed by the bypass capacitor connections, the

VIN pins, and the TPS54350 ground pins. The minimum

recommended bypass capacitance is 10-ÂµF ceramic with

a X5R or X7R dielectric and the optimum placement is

closest to the VIN pins and the AGND and PGND pins. See

Figure 21 for an example of a board layout. The AGND and

PGND pins should be tied to the PCB ground plane at the

pins of the IC. The source of the low-side MOSFET and the

anode of the Schottky diode should be connected directly

to the PCB ground plane. The PH pins should be tied

together and routed to the drain of the low-side MOSFET

or to the cathode of the external Schottky diode. Since the

PH connection is the switching node, the MOSFET (or

diode) should be located very close to the PH pins, and the

area of the PCB conductor minimized to prevent excessive

capacitive coupling. The recommended conductor width

from pins 14 and 15 is 0.050 inch to 0.075 inch of 1-ounce

copper. The length of the copper land pattern should be no

more than 0.2 inch.

For operation at full rated load, the analog ground plane

must provide adequate heat dissipating area. A 3-inch by

3-inch plane of copper is recommended, though not

mandatory, dependent on ambient temperature and

airflow. Most applications have larger areas of internal

ground plane available, and the PowerPAD should be

connected to the largest area available. Additional areas

on the bottom or top layers also help dissipate heat, and

any area available should be used when 3 A or greater

operation is desired. Connection from the exposed area of

the PowerPAD to the analog ground plane layer should be

made using 0.013-inch diameter vias to avoid solder

wicking through the vias. Four vias should be in the

PowerPAD area with four additional vias outside the pad

area and underneath the package. Additional vias beyond

those recommended to enhance thermal performance

should be included in areas not under the device package.

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