TPS40056 Datasheet, PDF (13/31 Pages) Texas Instruments – WIDE-INPUT SYNCHRONOUS, TRACKING BUCK CONTROLLER

TPS40056
APPLICATION INFORMATION
SLVS612 − APRIL 2006
LOOP COMPENSATION
Voltage-mode buck-type converters are typically compensated using Type III networks. Since the TPS40056
includes no voltage feedforward control, the gain of the PWM modulator must be included. The modulator gain
is described in Figure 5.
A_MOD
+
V_IN
V_S
ǒ Ǔ or
A_MOD(dB) + 20
log
V_IN
V_S
(14)
Duty dycle, D, varies from 0 to 1 as the control voltage, V_C, varies from the minimum ramp voltage to the
maximum ramp voltage, V_S. Also, for a synchronous buck converter, D = V_O / V_IN. To get the control voltage
to output voltage modulator gain in terms of the input voltage and ramp voltage,
D
+
V_O
V_IN
+
V_C
V_S
or
V_O
V_C
+
V_IN
V_S
(15)
Calculate the Poles and Zeros
For a buck converter using voltage mode control there is a double pole due to the output L-C_O. The double pole
is located at the frequency calculated in equation (16).
f_LC + _2p
1
Ǹ_L
(Hertz)
C_O
(16)
There is also a zero created by the output capacitance, C_O, and its associated ESR. The ESR zero is located
at the frequency calculated in equation (17).
f_Z + _2p
1
ESR
C_O ^(Hertz)
(17)
Calculate the value of R_BIAS to set the output voltage, V_OUT.
R_BIAS
+
V_{EA_REF} R1
V_OUT * V_{EA_REF}
W
(18)
The maximum crossover frequency (0 dB loop gain) is calculated in equation (19).
f_C
+
f_SW
4
(Hertz)
(19)
Typically, f_C is selected to be close to the midpoint between the L-C_O double pole and the ESR zero. At this
frequency, the control to output gain has a –2 slope (−40 dB/decade), while the Type III topology has a +1 slope
(20 dB/decade), resulting in an overall closed loop –1 slope (−20 dB/decade).
Figure 5 shows the modulator gain, L-C filter, output capacitor ESR zero, and the resulting response to be
compensated.
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