TLV5608_15 Datasheet, PDF (13/23 Pages) Texas Instruments – 8-CHANNEL, 12-/10-/8-BIT, 2.7-V TO 5.5-V LOW POWER DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN

TLV5608
TLV5610
TLV5629
www.ti.com.................................................................................................................................................... SLAS268G – MAY 2000 – REVISED NOVEMBER 2008
DAC A-H AND TWO-CHANNEL REGISTERS
Writing to DAC A-H sets the output voltage of channel A-H. It is possible to automatically generate the
complement of one channel by writing to one of the four two-channel registers (DAC A and B etc.).
The TLV5610 decodes all 12 data bits. The TLV5608 decodes D11 to D2 (D1 and D0 are ignored). The TLV5629
decodes D11 to D4 (D3 to D0 are ignored).
PRESET
The outputs of the DAC channels can be driven simultaneously to a predefined value stored in the preset register
by driving the PRE input pin low and asserting the LDAC input pin. The preset register is cleared (set to zero) by
the POR circuit after power up. Therefore, it must be written with a predefined value before asserting the PRE
pin low, unless zero is the desired preset value. The PRE input is asynchronous to the clock.
CTRL0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
X
X
X
PD
DO
X
X
IM
PD : Full device power down
DO : Digital output enable
IM : Input mode
X
: Reserved
0 = normal
0 = disable
0 = straight binary
1 = power down
1 = enable
1 = twos complement
If DOUT is enabled, the data input on DIN is output on DOUT with a 16-cycle delay. That makes it possible to
daisy-chain multiple DACs on one serial bus.
CTRL1
D11
D10
D9
X
X
X
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
P_GH
P_EF
P_CD
P_AB
S_GH
S_EF
S_CD
S_AB
P_XY : Power down DAC_XY 0 = normal
S_XY : Speed DAC_XY
0 = slow
XY : DAC pair AB, CD, EF, or GH
1 = power down
1 = fast
In power-down mode, the amplifiers of the selected DAC pair within the device are disabled and the total power
consumption of the device is significantly reduced. Power-down mode of a specific DAC pair can be selected by
setting the PXY bit within the data word to 1.
There are two settling time modes: fast and slow. Fast mode of a DAC pair is selected by setting S_XY to 1 and
slow mode is selected by setting S_XY to 0.
REFERENCE
The DAC reference can be sourced externally using precision reference circuits. Since the reference input is
buffered, it can be connected to the supply voltage.
BUFFERED AMPLIFIER
The DAC outputs are buffered by an amplifier with a gain of two, which are configurable as Class A (fast mode)
or Class AB (slow or low-power mode). The output buffers have near rail-to-rail output with short-circuit
protection, and can reliably drive a 2-kΩ load with a 100-pF load capacitance.
Copyright © 2000–2008, Texas Instruments Incorporated
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