TLV1571 Datasheet, PDF (13/29 Pages) Texas Instruments – 2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT, PARALLEL ANALOG-TO-DIGITAL CONVERTERS

software START conversion (continued)
internal clock
With CS low and WR low, data is written into the ADC. Sampling begins at the rising edge of WR. Conversion begins 6 clocks after sampling
begins. The internal clock begins at the rising edge of WR. The internal clock is disabled after each conversion. Subsequent sampling begins
at the rising edge of RD.
t _{su(CSL_WRL)}
CS
t _{su(CSL_RDL)}
t _{h(RDH_CSH)}
t _{h(WRH_CSH)}
WR
RD
t _(STARTOSC)
t _(STARTOSC)
04
5
6
15
04
5
15
INTCLK
t(sample)
(Channel 0)
(see Note A)
t _{su(DAV_WRH)}
t _{h(WRH_DAV)}
tc
t(sample)
(Channel 1)
(see Note A)
t _{dis(RDH_DAV)}
tc
D[0:9]
Config
Data
ADC
Data
ADC
t _{en(RDL_DAV)}
INT
OR
EOC
Auto Powerdown
NOTE A: AIN for TLV1571; channels sweep according to register settings.
Figure 7. Multichannel Input Mode Conversion – Software Start, Internal Clock
Auto Powerdown