MSP430X22X2_10 Datasheet, PDF (13/87 Pages) Texas Instruments – MIXED SIGNAL MICROCONTROLLER

MSP430x22x2, MSP430x22x4
MIXED SIGNAL MICROCONTROLLER
SLAS504D -- JULY 2006 -- REVISED MARCH 2010
interrupt vector addresses
The interrupt vectors and the power-up starting address are located in the address range of 0FFFFh to 0FFC0h.
The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence.
If the reset vector (located at address 0FFFEh) contains 0FFFFh (e.g., flash is not programmed) the CPU goes
into LPM4 immediately after power up.
INTERRUPT SOURCE
INTERRUPT FLAG
SYSTEM INTERRUPT WORD ADDRESS
PRIORITY
Power-up
External reset
Watchdog
Flash key violation
PC out-of-range (see Note 1)
PORIFG
RSTIFG
WDTIFG
KEYV
(see Note 2)
Reset
0FFFEh
31, highest
NMI
NMIIFG
(non)-maskable,
Oscillator fault
OFIFG
(non)-maskable,
0FFFCh
30
Flash memory access violation
ACCVIFG
(non)-maskable
(see Notes 2 & 4)
Timer_B3
TBCCR0 CCIFG (see Note 3)
maskable
0FFFAh
29
Timer_B3
TBCCR1 and TBCCR2
CCIFGs, TBIFG
maskable
0FFF8h
28
(see Notes 2 and 3)
0FFF6h
27
Watchdog Timer
WDTIFG
maskable
0FFF4h
26
Timer_A3
TACCR0 CCIFG (see Note 3)
maskable
0FFF2h
25
Timer_A3
TACCR1 CCIFG.
TACCR2 CCIFG
maskable
0FFF0h
24
TAIFG (see Notes 2 and 3)
USCI_A0/USCI_B0 Receive
UCA0RXIFG, UCB0RXIFG
(see Notes 2)
maskable
0FFEEh
23
USCI_A0/USCI_B0 Transmit
UCA0TXIFG, UCB0TXIFG
(see Notes 2)
maskable
0FFECh
22
ADC10
ADC10IFG (see Note 3)
maskable
0FFEAh
21
0FFE8h
20
I/O Port P2
(eight flags)
P2IFG.0 to P2IFG.7
(see Notes 2 and 3)
maskable
0FFE6h
19
I/O Port P1
(eight flags)
P1IFG.0 to P1IFG.7
(see Notes 2 and 3)
maskable
0FFE4h
18
0FFE2h
17
0FFE0h
16
(see Note 5)
(see Note 6)
0FFDEh
0FFDCh ... 0FFC0h
15
14 ... 0, lowest
NOTES:
1. A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh) or
from within unused address ranges.
2. Multiple source flags
3. Interrupt flags are located in the module.
4. (non)-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot.
Nonmaskable: neither the individual nor the general interrupt-enable bit will disable an interrupt event.
5. This location is used as bootstrap loader security key (BSLSKEY).
A 0AA55h at this location disables the BSL completely.
A zero (0h) disables the erasure of the flash if an invalid password is supplied.
6. The interrupt vectors at addresses 0FFDCh to 0FFC0h are not used in this device and can be used for regular program code if
necessary.
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