LP38853 Datasheet, PDF (13/28 Pages) Texas Instruments – LP38853 3A Fast-Response High-Accuracy Adjustable LDO Linear Regulator with Enable and Soft-Start

LP38853
www.ti.com
SNVS335D – DECEMBER 2006 – REVISED APRIL 2013
It is recommended that the values selected for R1 and R2 are such that the parallel value is less than 10 kΩ.
This is to prevent internal parasitic capacitances on the ADJ pin from interfering with the F_Z pole set by R1 and
C_FF.
( (R1 x R2) / (R1 + R2) ) ≤ 10 kΩ
(6)
Table 1 lists some suggested, best fit, standard ±1% resistor values for R1 and R2, and a standard ±10%
capacitor values for C_FF, for a range of V_OUT values. Other values of R1, R2, and C_FF are available that will give
similar results.
V_OUT
0.8V
0.9V
1.0V
1.1V
1.2V
1.3V
1.4V
1.5V
1.6V
1.7V
1.8V
R1
1.07 kΩ
1.50 kΩ
1.00 kΩ
1.65 kΩ
1.40 kΩ
1.15 kΩ
1.07 kΩ
2.00 kΩ
1.65 kΩ
2.55 kΩ
2.94 kΩ
Table 1.
R2
1.78 kΩ
1.87 kΩ
1.00 kΩ
1.37 kΩ
1.00 kΩ
715 Ω
590 Ω
1.00 kΩ
750 Ω
1.07 kΩ
1.13 kΩ
C_FF
12 nF
8.2 nF
12 nF
8.2 nF
10 nF
12 nF
12 nF
6.8 nF
8.2 nF
5.6 nF
4.7 nF
F_Z
12.4 kHz
12.9 kHz
13.3 kHz
11.8 kHz
11.4 kHz
11.5 kHz
12.4 kHz
11.7 kHz
11.8 kHz
11.1 kHz
11.5 kHz
Please refer to the TI AN-1378 Application Report for additional information on how resistor tolerances affect the
calculated V_OUT value.
INPUT VOLTAGE
The input voltage (V_IN) is the high current external voltage rail that will be regulated down to a lower voltage,
which is applied to the load. The input voltage must be at least V_OUT + V_DO, and no higher than whatever value is
used for V_BIAS.
For applications where V_BIAS is higher than 4.5V, V_IN must be no greater than 4.5V, otherwise output voltage
accuracy may be affected.
BIAS VOLTAGE
The bias voltage (V_BIAS) is a low current external voltage rail required to bias the control circuitry and provide
gate drive for the N-FET pass transistor. When V_OUT is set to 1.20V, or less, V_BIAS may be anywhere in the
operating range of 3.0V to 5.5V. If V_OUT is set higher than 1.20V , V_BIAS must be between 4.5V and 5.5V to
ensure proper operation of the device.
UNDER VOLTAGE LOCKOUT
The bias voltage is monitored by a circuit which prevents the device from functioning when the bias voltage is
below the Under-Voltage Lock-Out (UVLO) threshold of approximately 2.45V.
As the bias voltage rises above the UVLO threshold the device control circuitry becomes active. There is
approximately 150 mV of hysteresis built into the UVLO threshold to provide noise immunity.
When the bias voltage is between the UVLO threshold and the Minimum Operating Rating value of 3.0V the
device will be functional, but the operating parameters will not be within the specified limits.
SUPPLY SEQUENCING
There is no requirement for the order that V_IN or V_BIAS are applied or removed.
One practical limitation is that the Soft-Start circuit starts charging C_SS when both V_BIAS rises above the UVLO
threshold and the Enable pin is above the V_EN(ON) threshold. If the application of V_IN is delayed beyond this point
the benefits of Soft-Start will be compromised.
Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: LP38853
Submit Documentation Feedback
13