DS90C031WGRQMLV Datasheet, PDF (13/21 Pages) Texas Instruments – DS90C031QML LVDS Quad CMOS Differential Line Driver

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DS90C031QML
SNLS202B – MARCH 2006 – REVISED MARCH 2013
Figure 32. Driver Output Levels
Pin Descriptions
Pin No. (SOIC)
1, 7, 9, 15
2, 6, 10, 14
3, 5, 11, 13
4
12
16
8
Name
D_I
D_O+
D_O−
EN
EN*
V_CC
Gnd
Description
Driver input pin, TTL/CMOS compatible
Non-inverting driver output pin, LVDS levels
Inverting driver output pin, LVDS levels
Active high enable pin, OR-ed with EN*
Active low enable pin, OR-ed with EN
Power supply pin, +5V ± 10%
Ground pin
Radiation Environments
Careful consideration should be given to environmental conditions when using a product in a radiation
environment.
Total Ionizing Dose
Radiation hardness assured (RHA) products are those part numbers with a total ionizing dose (TID) level
specified in the Ordering Information table on the front page. Testing and qualification of these products is done
on a wafer level according to MIL-STD-883G, Test Method 1019.7, Condition A and the “Extended room
temperature anneal test” described in section 3.11 for application environment dose rates less than 0.16
rad(Si)/s. Wafer level TID data is available with lot shipments.
Single Event Latch-Up
One time single event latch-up (SEL) testing was preformed showing SEL immunity to 103 MeV-cm²/mg. A test
report is available upon request.
Single Event Upset
Single event upset (SEU) data are available upon request.
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