DRV8825 Datasheet, PDF (13/22 Pages) Texas Instruments – STEPPER MOTOR CONTROLLER IC

DRV8825
www.ti.com
SLVSA73C – APRIL 2010 – REVISED MAY 2011
Table 3. Relative Current and Step Directions (continued)
1/32 STEP 1/16 STEP 1/8 STEP 1/4 STEP 1/2 STEP
104
105
53
27
14
106
107
54
108
109
55
28
110
111
56
112
113
57
29
15
8
114
115
58
116
117
59
30
118
119
60
120
121
61
31
16
122
123
62
124
125
63
32
126
127
64
128
FULL
STEP
70%
4
WINDING
CURRENT
A
34%
38%
43%
47%
51%
56%
60%
63%
67%
71%
74%
77%
80%
83%
86%
88%
90%
92%
94%
96%
97%
98%
99%
100%
100%
WINDING
CURRENT
B
–94%
–92%
–90%
–88%
–86%
–83%
–80%
–77%
–74%
–71%
–67%
–63%
–60%
–56%
–51%
–47%
–43%
–38%
–34%
–29%
–24%
–20%
–15%
–10%
–5%
ELECTRICAL
ANGLE
290
293
295
298
301
304
307
309
312
315
318
321
323
326
329
332
335
338
340
343
346
349
352
354
357
nRESET, nENBLE and nSLEEP Operation
The nRESET pin, when driven active low, resets internal logic, and resets the step table to the home position. It
also disables the H-bridge drivers. The STEP input is ignored while nRESET is active.
The nENBL pin is used to control the output drivers and enable/disable operation of the indexer. When nENBL is
low, the output H-bridges are enabled, and rising edges on the STEP pin are recognized. When nENBL is high,
the H-bridges are disabled, the outputs are in a high-impedance state, and the STEP input is ignored.
Driving nSLEEP low will put the device into a low power sleep state. In this state, the H-bridges are disabled, the
gate drive charge pump is stopped, the V3P3OUT regulator is disabled, and all internal clocks are stopped. In
this state all inputs are ignored until nSLEEP returns inactive high. When returning from sleep mode, some time
(approximately 1 ms) needs to pass before applying a STEP input, to allow the internal circuitry to stabilize. Note
that nRESET and nSLEEP have internal pulldown resistors of approximately 100 kΩ. These signals need to be
driven to logic high for device operation.
Protection Circuits
The DRV8825 is fully protected against undervoltage, overcurrent and overtemperature events.
Overcurrent Protection (OCP)
An analog current limit circuit on each FET limits the current through the FET by removing the gate drive. If this
analog current limit persists for longer than the OCP time, all FETs in the H-bridge will be disabled and the
nFAULT pin will be driven low. The device will remain disabled until either nRESET pin is applied, or VM is
removed and re-applied.
Copyright © 2010–2011, Texas Instruments Incorporated
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