DAC3151 Datasheet, PDF (13/57 Pages) Texas Instruments – Single 14-/12-/10-Bit 500 MSPS Digital-to-Analog Converters

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DAC3151
DAC3161
DAC3171
SLAS959A – AUGUST 2013 – REVISED AUGUST 2013
PIN ASSIGNMENT TABLE – DAC3171 14-BIT INTERFACE MODE (continued)
PIN
NAME
NO.
DATA INTERFACE
DATA[13:0]P/N
9/10-
19/20
22/23
26/27,
29/30-
39/40
DATACLKP/N
SYNCP/N
ALIGNP/N
24/25
6/7
4/5
OUTPUT/CLOCK
DACCLKP/N
1/2
IOUTAP/N
61/60
REFERENCE
EXTIO
58
BIASJ
57
POWER SUPPLY
IOVDD
45
CLKVDD18
3
DIGVDD18
21, 28
VDDA18
50, 64
VDDA33
55, 56,
59
VFUSE
8
NC
51, 52,
53, 54
62, 63
I/O
DESCRIPTION
I LVDS input data bits for both channels. Each positive/negative LVDS pair has an internal 100 Ω
termination resistor. Data format relative to DATACLKP/N clock is Double Data Rate (DDR) with two data
transfers per DATACKP/N clock cycle.
The data format is interleaved with channel A (rising edge) and channel B falling edge.
In the default mode (reverse bus not enabled):
DATA13P/N is most significant data bit (MSB)
DATA0P/N is most significant data bit (LSB)
I DDR differential input data clock. Edge to center nominal timing. Ch A rising edge, Ch B falling edge in
multiplexed output mode.
I Reset the FIFO or to be used as a syncing source. These two functions are captured with the rising edge
of DATACLKP/N. The signal captured by the falling edge of DATACLKP/N.
I LVPECL FIFO output syncrhonization. This positive/negative pair is captured with the rising edge of
DACCLKP/N. It is used to reset the clock dividers and for multiple DAC synchronization. If unused it can
be left unconnected.
I LVPECL clock input for DAC core with a self-bias of approximately CLKVDD18/2.
O A-Channel DAC current output. An offset binary data pattern of 0x0000 at the DAC input results in a full
scale current source and the most positive voltage on the IOUTAP pin. Similarly, a 0xFFFF data input
results in a 0 mA current source and the least positive voltage on the IOUTAP pin.
I/O Used as external reference input when internal reference is disabled. Requires a 0.1 µF decoupling
capacitor to GND when used as reference output.
O Full-scale output current bias. For 20 mA full-scale output current, connect a 960 Ω resistor to GND.
I Supply voltage for CMOS IO’s. 1.8V – 3.3V.
I 1.8V clock supply
I 1.8V digital supply. Also supplies LVDS receivers.
I Analog 1.8V supply
I Analog 3.3V supply
I Digital supply voltage. (1.8V) This supply pin is also used for factory fuse programming. Connect to
DVDD pins for normal operation.
Not Used. These pins can be left open or tied to GROUND in actual application use.
PRODUCT
DAC3151
DAC3161
DAC3171
PACKAGE-
LEAD
QFN-64
PACKAGE/ORDERING INFORMATION⁽¹⁾
PACKAGE
DESIGNATOR
SPECIFIED
TEMPERATUR
E RANGE
ECO PLAN
LEAD/BALL
FINISH
ODERING
NUMBER
DAC3151IRGCT
DAC3151IRGCR
RGC
–40°C to 85°C
GREEN (RoHS
and no Sb/Br)
NiPdAu
DAC3161IRGCT
DAC3161IRGCR
DAC3171IRGCT
DAC3171IRGCR
TRANSPORT
MEDIA
Tape and Reel
QUANTITY
250
2000
250
2000
250
2000
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
Copyright © 2013, Texas Instruments Incorporated
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