CD54HC190 Datasheet, PDF (13/26 Pages) Texas Instruments – SYNCHRONOUS UP/DOWN COUNTERS WITH DOWN/UP MODE CONTROL

CD54HC190, CD74HC190
CD54HC191, CD74HC191, CD54HCT191, CD74HCT191
SYNCHRONOUS UP/DOWN COUNTERS WITH DOWN/UP MODE CONTROL
SCHS275E − MARCH 2002 − REVISED OCTOBER 2003
’HC190, ’HC191 timing requirements over recommended operating free-air temperature range
(unless otherwise noted) (see Figure 4)
VCC
TA = 25°C
MIN MAX
TA = −55°C
TO 125°C
MIN MAX
TA = −40°C
TO 85°C
MIN MAX
UNIT
fclock Clock frequency†
2V
4.5 V
6V
6
4
5
30
20
25 MHz
35
23
29
tw
Pulse duration
LOAD low
CLK high or low
2V
80
120
100
4.5 V
16
24
20
6V
14
20
17
ns
2V
100
150
125
4.5 V
20
30
25
6V
17
26
21
2V
60
90
75
Data before LOAD↑
4.5 V
12
18
15
6V
10
15
13
2V
60
90
75
tsu
Setup time
CTEN before CLK↑
4.5 V
12
18
15
ns
6V
10
15
13
2V
90
135
115
D/U before CLK↑
4.5 V
18
27
23
6V
15
23
20
2V
2
2
2
Data before LOAD↑
4.5 V
2
2
2
6V
2
2
2
th
Hold time
2V
2
2
2
CTEN before CLK↑
4.5 V
2
2
2
ns
6V
2
2
2
2V
0
0
0
D/U before CLK↑
4.5 V
0
0
0
6V
0
0
0
2V
60
90
75
trec Recovery time
LOAD inactive before CLK↑ 4.5 V
12
18
15
ns
6V
10
15
13
† _{Applies to noncascaded operation only. With cascaded counters, clock-to-terminal count propagation delays, CTEN-to-clock setup times, and}
CTEN-to-clock hold times determine maximum clock frequency. For example, with these HC devices:
f_max(CLK)
+
CLK-to-MAXńMIN
propagation
delay
)
1
CTEN-to-CLK
setup
time
)
CTEN-to-CLK
hold
time
+
42
)
1
12
)
2
[
18
MHz
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