BQ32000 Datasheet, PDF (13/20 Pages) Texas Instruments – REAL-TIME CLOCK (RTC)

bq32000
www.ti.com................................................................................................................................................... SLUS900B – DECEMBER 2008 – REVISED JUNE 2009
Address
Name
Initial Value
Description
D7
OUT
r/w
1
UC
OUT
FT
S
CAL
0x07
CAL_CFG1
10000000b
Calibration and control
CAL_CFG1 Register
D6
D5
D4
D3
D2
D1
D0
BIT(S)
FT
S
CAL
Name
r/w
r/w
r/w
Read/Write
0
0
0
0
0
0
0
Initial
UC
UC
UC
UC
UC
UC
UC
Cycle
Logic output, when FT = 0. When FT is zero, the logic output of IRQ pin reflects the value of OUT.
0
IRQ is logic 0
1
IRQ is logic 1
Frequency test. The FT bit is used to enable the frequency test signal on the IRQ pin. When FT is 1, a square wave is
produced on the IRQ pin. The FTF bit in the SFR register determines the frequency of the test signal.
0
Disable
1
Enable
Calibration sign. The S bit determines the polarity of the calibration applied to the oscillator. If S is 0, then the calibration
slows the RTC. If S is 1, then the calibration speeds the RTC.
0
Slowing (+)
1
Speeding (–)
Calibration. The CAL bits along with S determine the calibration amount as shown in Table 5.
CAL (DEC)
0
1
N
30
31
Table 5. Calibration
S=0
+0 ppm
+2 ppm
+N / 491520 (per minute)
+61 ppm
+63 ppm
S=1
–0 ppm
–4 ppm
–N / 245760 (per minute)
–122 ppm
–126 ppm
Address
Name
Initial Value
Description
0x08
TCH2
10010000b
Trickle charge TCH2 control
TCH2 Register
D7
D6
D5
D4
RSVD
TCH2
r/w
r/w
1
0
0
1
UC
0
0
1
D3
D2
D1
RSVD
r/w
0
0
0
UC
UC
UC
D0
BIT(S)
Name
Read/Write
0
Initial
UC
Cycle
RSVD
TCH2
Reserved. The RSVD bits should always be written as 0.
Trickle charge switch two. The TCH2 bit determines if the internal trickle charge switch is closed or open. All the trickle
charge switches must be closed in order for trickle charging to occur. If TCH2 is 0, then the TCH2 switch is open. If
TCH2 is 1, then the TCH2 switch is closed.
0
Open
1
Closed
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