AFE5809_13 Datasheet, PDF (13/90 Pages) Texas Instruments – Fully Integrated, 8-Channel Ultrasound Analog Front End with Passive CW Mixer, and Digital I/Q Demodulator, 0.75 nV/rtHz, 14, 12-Bit, 65 MSPS, 158 mW/CH

AFE5809
www.ti.com
SLOS738C – SEPTEMBER 2012 – REVISED JANUARY 2013
DIGITAL CHARACTERISTICS
Typical values are at +25°C, AVDD = 3.3V, AVDD_5 = 5V and AVDD_ADC = 1.8V, DVDD = 1.8V unless otherwise noted.
Minimum and maximum values are across the full temperature range: T_MIN = 0°C to T_MAX = +85°C,.
PARAMETER
CONDITION
MIN
TYP
MAX UNITS⁽¹⁾
DIGITAL INPUTS/OUTPUTS
V_IH Logic high input voltage
V_IL
Logic low input voltage
Logic high input current
2
0
200
3.3
V
0.3
V
µA
Logic low input current
200
µA
Input capacitance
5
pF
V_OH Logic high output voltage
V_OL Logic low output voltage
LVDS OUTPUTS
SDOUT pin
SDOUT pin
DVDD
V
0
V
Output differential voltage
with 100 ohms external differential
termination
400
mV
Output offset voltage
Common-mode voltage
1100
mV
FCLKP and FCLKM
1X clock rate
10
65 MHz
DCLKP and DCLKM
7X clock rate
70
455 MHz
t_su
Data setup time⁽²⁾
t_h
Data hold time⁽²⁾
ADC INPUT CLOCK
6X clock rate
60
350
350
390 MHz
ps
ps
CLOCK frequency
10
65 MSPS
Clock duty cycle
45%
50%
55%
Clock input amplitude,
differential(V_{CLKP_ADC}–V_{CLKM_ADC})
Sine-wave, ac-coupled
LVPECL, ac-coupled
LVDS, ac-coupled
0.5
Vpp
1.6
Vpp
0.7
Vpp
Common-mode voltage
biased internally
1
V
Clock input amplitude V_{CLKP_ADC} (single-
ended)
CMOS CLOCK
1.8
Vpp
(1) The DC specifications refer to the condition where the LVDS outputs are not switching, but are permanently at a valid logic level 0 or 1
with 100Ω external termination.
(2) Setup and hold time specifications take into account the effect of jitter on the output data and clock. These specifications also assume
that the data and clock paths are perfectly matched within the receiver. Any mismatch in these paths within the receiver would appear
as reduced timing margins
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