SM320F2810-EP_101 Datasheet, PDF (128/158 Pages) Texas Instruments – Digital Signal Processors

Electrical Specifications
See Notes A and B
Lead
Active
WS (Synch)
Trail
See Note C
XCLKOUT=XTIMCLK
XCLKOUT=1/2 XTIMCLK
XZCS0AND1, XZCS2,
XZCS6AND7
XA[0:18]
XRD
XWE
XR/W
XD[0:15]
t_{d(XCOH-XZCSL)}
t_d(XCOH-XA)
t_{d(XCOHL-XRDL)}
t_su(XD)XRD
t_a(XRD)
t_a(A)
t_{su(XRDYsynchL)XCOHL}
t_{d(XCOHL-XZCSH)}
t_{d(XCOHL-XRDH)}
t_h(XD)XRD
DIN
XREADY(Synch)
t_{h(XRDYsynchL)}
t_{su(XRDHsynchH)XCOHL}
t_{e(XRDYsynchH)}
t_{h(XRDYsynchH)XZCSH}
See Note D
See Note E
Legend:
= Don’t care. Signal can be high or low during this time.
NOTES: A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device will insert an
alignment cycle before an access to meet this requirement.
B. During alignment cycles, all signals will transition to their inactive state.
C. During inactive cycles, the XINTF address bus will always hold the last address put out on the bus. This includes
alignment cycles.
D. For each sample, setup time from the beginning of the access (D) can be calculated as:
D = (XRDLEAD + XRDACTIVE +n − 1) t_c(XTIM) − t_{su(XRDYsynchL)XCOHL}
E. Reference for the first sample is with respect to this point
E = (XRDLEAD + XRDACTIVE) t_c(XTIM)
where n is the sample number: n = 1, 2, 3, and so forth.
Figure 6−31. Example Read With Synchronous XREADY Access
XTIMING register parameters used for this example:
XRDLEAD
XRDACTIVE
XRDTRAIL USEREADY
X2TIMING
≥1
3
≥1
1
0
† _{N/A = “Don’t care” for this example}
XWRLEAD
N/A^†
XWRACTIVE
N/A^†
XWRTRAIL
N/A^†
READYMODE
0 = XREADY
(Synch)
128 SGUS051B
March 2004 − Revised April 2010