SM320DM642-EP Datasheet, PDF (128/170 Pages) Texas Instruments – Video/Imaging Fixed Point Digital Signal Processor

SM320DM642-EP
Video/Imaging Fixed Point Digital Signal Processor
SGUS058B – JUNE 2007 – REVISED JANUARY 2008
5.12.3 PCI Electrical Data/Timing
5.12.3.1 Peripheral Component Interconnect (PCI) Timing
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Table 5-42. Timing Requirements for PCLK⁽¹⁾⁽²⁾ (see Figure 5-46)
–500, A-600
–600, –720
NO.
[33 MHz]
[66 MHz]
MIN MAX
MIN MAX
1 t_c(PCLK)
Cycle time, PCLK
30 (or 4P⁽³⁾)
15 (or 4P⁽³⁾)
2 t_w(PCLKH)
Pulse duration, PCLK high
11
6
3 t_w(PCLKL)
Pulse duration, PCLK low
11
6
4 t_sr(PCLK)
Δv/Δt slew rate, PCLK
1
4
1.5
4
(1) For 3.3-V operation, the reference points for the rise and fall transitions are measured at V_ILP MAX and V_IHP MIN.
(2) P = 1/CPU clock frequency in ns. For example when running parts at 720 MHz,use P = 1.39 ns.
(3) Select the parameter value, whichever is larger.
UNIT
ns
ns
ns
V/ns
1
4
2
0.4 DV_DD V MIN
Peak to Peak for
3.3V signaling
PCLK
3
4
Figure 5-46. PCLK Timing
Table 5-43. Timing Requirements for PCI Reset (see Figure 5-47)
NO.
1
t_w(PRST)
2
t_{su(PCLKA-PRSTH)}
Pulse duration, PRST
Setup time, PCLK active before PRST high
–500
–600
–720
MIN MAX
1
100
UNIT
ms
µs
PCLK
1
PRST
2
Figure 5-47. PCI Reset (PRST) Timing
NO.
4
t_su(IV-PCLKH)
5
t_h(IV-PCLKH)
Table 5-44. Timing Requirements for PCI Inputs (see Figure 5-48)
Setup time, input valid before PCLK high
Hold time, input valid after PCLK high
–500, A-600
33 MHz
MIN MAX
7
0
–600
–720
66 MHz
MIN MAX
3
0
UNIT
ns
ns
128 DM642 Peripheral Information and Electrical Specifications
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