TPS560200DBVR Datasheet, PDF (12/18 Pages) Texas Instruments – 4.5V to 17V Input, 500mA Synchronous Step Down SWIFT Converter with Advanced Eco-mode

TPS560200
SLVSC81 – SEPTEMBER 2013
LAYOUT GUIDELINES
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The VIN pin should be bypassed to ground with a low ESR ceramic bypass capacitor. Care should be taken to
minimize the loop area formed by the bypass capacitor connection. the VIN pin, and the GND pin of the IC. The
typical recommended bypass capacitance is 10-μF ceramic with a X5R or X7R dielectric and the optimum
placement is closest to the VIN and GND pins of the device. An additional high frequency bypass capacitor may
be added. See Figure 19 for a PCB layout example. The GND pin should be tied to the PCB ground plane at the
pin of the IC. The PH pin should be routed to a small copper area directly adjacent to the pin. Make the
circulating loop from PH to the output inductor, output capacitors and back to GND as tight as possible while
preserving adequate etch width to reduce conduction losses in the copper. Connect the exposed thermal pad to
bottom or internal layer ground plane using vias as shown. Additional vias may be used adjacent to the IC to tie
top side copper to the internal or bottom layer copper. The additional external components can be placed
approximately as shown. It may be possible to obtain acceptable performance with alternate layout schemes,
however this layout has been shown to produce good results and is intended as a guideline.
VIN
VIN
INPUT
BYPASS
CAPACITOR
GND
VIN
HIGH FREQENCY
BYPASS
CAPACITOR
VIN
VSENSE
GND
PH
GND
EN
FEEDBACK
RESISTORS
OPTIONAL
FEED FORWARD
CAPACITOR
OUTPUT
INDUCTOR
VOUT
TO ENABLE
CONTROL
OUTPUT
FILTER
CAPACITOR
GND
VIA to Ground Plane
Figure 19. Typical Layout
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