TPS51116 Datasheet, PDF (12/29 Pages) Texas Instruments – COMPLETE DDR AND DDR2 MEMORY POWER SOLUTION SYNCHRONOUS BUCK CONTROLLER, 3-A LDO, BUFFERED REFERENCE

TPS51116
SLUS609A – MAY 2004 – REVISED JUNE 2004
DETAILED DESCRIPTION (continued)
Table 3. Discharge Selection
MODE
V5IN
VDDQ
S4/GND
DISCHARGE MODE
No discharge
Tracking discharge
Non-tracking discharge
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When in tracking-discharge mode, TPS51116 discharges outputs through the internal VTT regulator transistors
and VTT output tracks half of VDDQ voltage during this discharge. Note that VDDQ discharge current flows via
VLDOIN to LDOGND thus VLDOIN must be connected to VDDQ output in this mode. The internal LDO can
handle up to 3 A and discharge quickly. After VDDQ is discharged down to 0.2 V, the internal LDO is turned off
and the operation mode is changed to the non-tracking-discharge mode.
When in non-tracking-discharge mode, TPS51116 discharges outputs using internal MOSFETs which are
connected to VDDQSNS and VTT. The current capability of these MOSFETs are limited to discharge slowly.
Note that VDDQ discharge current flows from VDDQSNS to PGND in this mode. In case of non-tracking mode,
TPS51116 does not discharge output charge at all.
Current Protection for VDDQ
The SMPS has cycle-by-cycle over current limiting control. The inductor current is monitored during the OFF
state and the controller keeps the OFF state during the inductor current is larger than the over current trip level.
The trip level and current sense scheme are determined by CS pin connection (see Current Sensing Scheme
section). For resistor sensing scheme, the trip level, V_TRIP, is fixed value of 60 mV.
For R_DS(on) sensing scheme, CS terminal sinks 10 µA and the trip level is set to the voltage across this R_TRIP
resistor.
V_TRIP (mV) + R_TRIP (kW) 10 (mA)
(4)
As the comparison is done during the OFF state, V_TRIP sets valley level of the inductor current. Thus, the load
current at over current threshold, I_OCP, can be calculated as shown in Equation 5.
I_OCP
+
V_TRIP
R_DS(on)
)
I_RIPPLE
2
+
V_TRIP
R_DS(on)
)
2
1
L
f
ǒ_{VIN * VOUT}Ǔ
V_IN
V_OUT
(5)
In an overcurrent condition, the current to the load exceeds the current to the output capacitor thus the output
voltage tends to fall down. If the output voltage becomes less than Powergood level, the V_TRIP is cut into half and
the output voltage tends to be even lower. Eventually, it crosses the undervoltage protection threshold and
shutdown.
Current Protection for VTT
The LDO has an internally fixed constant over current limiting of 3.8 A while operating at normal condition. This
trip point is reduced to 2.2 A before the output voltage comes within ±5% of the target voltage or goes outside of
±10% of the target voltage.
Overvoltage and Undervoltage Protection for VDDQ
TPS51116 monitors a resistor divided feedback voltage to detect overvoltage and undervoltage. If VDDQSET is
connected to V5IN or GND, the feedback voltage is made by an internal resistor divider inside VDDQSNS pin. If
an external resistor divider is connected to VDDQSET pin, the feedback voltage is VDDQSET voltage itself.
When the feedback voltage becomes higher than 115% of the target voltage, the OVP comparator output goes
high and the circuit latches as the top MOSFET driver OFF and the bottom MOSFET driver ON.
Also, TPS51116 monitors VDDQSNS voltage directly and if it becomes greater than 4 V TPS51116 turns off the
top MOSFET driver. When the feedback voltage becomes lower than 70% of the target voltage, the UVP
comparator output goes high and an internal UVP delay counter begins counting. After 32 cycles, TPS51116
latches OFF both top and bottom MOSFETs. This function is enabled after 1007 cycles of SMPS operation to
ensure startup.
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