TPS40040 Datasheet, PDF (12/36 Pages) Texas Instruments – LOW PIN COUNT, LOW VIN (2.5 V TO 5.5 V) SYNCHRONOUS BUCK DC-TO-DC CONTROLLER WITH ENABLE

TPS40040, TPS40041
SLUS700B – MARCH 2006 – REVISED MARCH 2006
www.ti.com
APPLICATION INFORMATION (continued)
Pre-Bias Startup
The TPS40040/1 supports pre-biased output voltage applications. In cases where the output voltage is held up
by external means while the TPS40040/1 is off, full synchronous rectification is disabled during the initial phase
of soft starting the output voltage. When the first PWM pulses are detected during soft start, the controller slowly
initiates synshronous rectification by starting the synchronous rectifier with a narrow on time. It then increments
that on time on a cycle-by-cycle basis until it coincides with the time dictated by (1-D), where D is the duty cycle
of the converter. This approach prevents the sinking of current from a pre-biased output, and ensures the output
voltage startup and ramp to regulation is smooth and controlled.
NOTE:
If the output is pre-biased, PWM pulses start when the internal soft-start voltage rises
above the error amplifier input (FB pin).
Figure 20 below depicts the waveform of the HDRV and LDRV output signals at the beginning PWM pulses.
When HDRV turns off, diode rectification is enabled. Before the next PWM cycle starts, LDRV is turned on for a
short pulse. With every clock cycle, the leading edge of LDRV is modulated, increasing the on time of the
synchronous rectifier. Eventually, the leading edge of LDRV coincides with the falling edge of HDRV to achieve
full synchronous rectification. During normal operation of the converter, the TPS40040/1 operates in full two
quadrant source/sink mode.
Figure 21 shows the startup waveform of a 1.2-V output converter under three different pre-biased output
conditions. The lowest trace is when there is no pre-bias on the output. The center and top most traces indicate
converter startup with 0.5-V and 1.0-V pre-bias conditions.
V_IN = 5 V
V_OUT = 1.2 V
(200 mV/div)
PREBIAS = 1 V
V_HDRV
PREBIAS = 0.5 V
V_LDRV
PREBIAS = 0 V
t − Time − 2 µs/div
Figure 20. MOSFET Drivers at Beginning of Soft Start
t − Time − 500 µs/div
Figure 21. Startup Waveforms
The recommended output voltage pre-bias range is less than or equal to 90% of the final regulation voltage. A
pre-biased output voltage of 90% to 100% of final regulation could lead to the sinking of current from the pre-bias
source. If the pre-biased voltage is greater than the designed converter output regulation voltage, then upon the
completion of the soft-start interval, the TPS40040/1 draws current from the output to bring the output voltage
into regulation.
12