TMS320TCI6616 Datasheet, PDF (12/199 Pages) Texas Instruments – Communications Infrastructure KeyStone SoC

TMS320TCI6616
Communications Infrastructure KeyStone SoC
SPRS624A—January 2011
1.1 KeyStone Architecture
www.ti.com
TI’s KeyStone Multicore Architecture provides a high performance structure for integrating RISC and DSP cores
with application specific coprocessors and I/O. KeyStone is the first of its kind that provides adequate internal
bandwidth for nonblocking access to all processing cores, peripherals, coprocessors, and I/O. This is achieved with
four main hardware elements: Multicore Navigator, TeraNet, Multicore Shared Memory Controller, and
HyperLink.
Multicore Navigator is an innovative packet-based manager that controls 8192 queues. When tasks are allocated to
the queues, Multicore Navigator provides hardware-accelerated dispatch that directs tasks to the appropriate
available hardware. The packet-based system on a chip (SoC) uses the two Tbps capacity of the TeraNet switched
central resource to move packets. The Multicore Shared Memory Controller enables processing cores to access
shared memory directly without drawing from TeraNet’s capacity, so packet movement cannot be blocked by
memory access.
HyperLink provides a 50-Gbps chip-level interconnect that allows SoCs to work in tandem. Its low-protocol
overhead and high throughput make Hyperlink an ideal interface for chip-to-chip interconnections. Working with
Multicore Navigator, HyperLink dispatches tasks to tandem devices transparently and executes tasks as if they are
running on local resources.
1.2 Device Description
The TMS320TCI6616 Communications Infrastructure KeyStone SoC is a member of the C66xx SoC family based
on TI's new KeyStone Multicore SoC Architecture designed specifically for high performance wireless infrastructure
applications. The TCI6616 provides a very high performance macro basestation platform for developing all wireless
standards including WCDMA/HSPA/HSPA+, TD-SCDMA, GSM, TDD-LTE, FDD-LTE, and WiMAX. The
TCI6616 also sets a new standard for clock speed with operating frequencies up to 1.2 GHz.
TI's SoC architecture provides a programmable platform integrating various subsystems (C66x cores, IP network,
radio layers 1 and 2, and transport processing) and uses a queue-based communication system that allows the SoC
resources to operate efficiently and seamlessly. This unique SoC architecture also includes a TeraNet Switch that
enables the wide mix of system elements, from programmable cores to dedicated coprocessors and high speed IO,
to each operate at maximum efficiency with no blocking or stalling.
TI's new C66x core launches a new era of DSP technology by combining fixed point and floating point
computational capability in the processor without sacrificing speed, size, or power consumption. The
raw computational performance is an industry-leading 32 GMACS/core and 16 Gflops/core (@ 1.2 GHz operating
frequency). The C66x is also 100% backward compatible with software for C64x+ devices. The C66x core
incorporates 90 new instructions targeted for floating point (FPi) and vector math oriented (VPi) processing. These
enhancements yield tremendous performance improvements in multi-antenna 4.8G signal processing for
algorithms like MIMO and beamforming.
The TCI6616 contains many wireless basestation coprocessors to offload the bulk of the processing demands of
layer 1 and layer 2 base station processing. This keeps the cores free for receiver algorithms and other differentiating
functions. The SoC contains numerous copies of key coprocessors such as the FFTC and TCP3d. The architectural
elements of the SoC (Multicore Navigator) ensure that all the bits are processed without any CPU intervention or
overhead, allowing the system to make optimal use of its resources.
TI's scalable multicore SoC architecture solutions provide developers with a range of software- and
hardware-compatible devices to minimize development time and maximize reuse across all base station platforms
from Femto to Macro.
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