TLV320AIC28 Datasheet, PDF (12/81 Pages) Texas Instruments – STEREO AUDIO CODEC WITH INTERGRATED HEADPHONE AND SPEAKER AMPLIFIERS

TLV320AIC28
SLAS418A − FEBRUARY 2004 − REVISED SEPTEMBER 2004
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WCLK
BCLK
SDOUT
tL(BCLK)
th(WS)
tH(BCLK)
tP(BCLK)
ts(WS)
td(DO−WS)
SDIN
td(DO−BCLK)
ts(DI)
th(DI)
Figure 3. I²S/LJF/RJF Timing in Slave Mode
Typical Timing Requirements (see Figure 3)
PARAMETER(1)
IOVDD = 1.1 V
MIN MAX
tH(BCLK)
BCLK high period
tL(BCLK)
BCLK low period
ts(WS)
WCLK setup
th(WS)
WCLK hold
td (DO−WS)
WCLK to DOUT delay (for LJF mode)
td(DO−BCLK) BCLK to DOUT delay
ts(DI)
SDIN setup
th(DI)
SDIN hold
tr
Rise time
tr
Fall time
(1) _{These parameters are based on characterization and are not tested in production.}
40
40
6
6
30
30
6
6
5
5
IOVDD = 3.3 V
MIN MAX
35
35
6
6
18
15
6
6
4
4
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
12