TL2843B-Q1_15 Datasheet, PDF (12/18 Pages) Texas Instruments – HIGH-PERFORMANCE CURRENT-MODE PWM CONTROLLER

TL2843B-Q1
SLVSAE2A – JULY 2010 – REVISED FEBRUARY 2012
www.ti.com
Shutdown Technique
The PWM controller (see Figure 5) can be shut down by two methods: either raise the voltage at I_SENSE above
1 V or pull the COMP terminal below a voltage two diode drops above ground. Either method causes the output
of the PWM comparator to be high (see the Functional Block Diagram). The PWM latch is reset dominant so that
the output remains low until the next clock cycle after the shutdown condition at the COMP or I_SENSE terminal is
removed. In one example, an externally latched shutdown can be accomplished by adding an SCR that resets by
cycling V_CC below the lower UVLO threshold. At this point, the reference turns off, allowing the SCR to reset.
1 kΩ
V_REF
COMP
Shutdown
Shutdown
330 Ω
I_SENSE
500 Ω
To Current-Sense
Resistor
Figure 5. Shutdown Techniques
A fraction of the oscillator ramp can be summed resistively with the current-sense signal to provide slope
compensation for converters requiring duty cycles over 50% (see Figure 6). Note that capacitor C forms a filter
with R2 to suppress the leading-edge switch spikes.
V_REF
0.1 µF
R_T
R_T/C_T
I_SENSE
C_T
R1
R2
C
I_SENSE
R_SENSE
Figure 6. Slope Compensation
12
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