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SN75DP129 Datasheet, PDF (12/28 Pages) Texas Instruments – DisplayPort to TMDS Translator
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SN75DP129
SLAS583A – JANUARY 2008 – REVISED MARCH 2008
www.ti.com
TMDS and Main Link Pins
The main link inputs are designed to be compliant with the DisplayPort 1.1 specification. The TMDS outputs of
the SN75DP129 are designed to be compliant with the Digital Visual Interface 1.0 (DVI) and High Definition
Multimedia Interface 1.3 (HDMI) specifications. The differential output voltage swing can be fine-tuned with the
VSadj (TMDS-compliant Voltage Swing Control) resistor.
ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
VOH
VOL
VSWING
VOC(SS)
VOD(PP)
V(O)SBY
I(O)OFF
IOS
RINT
Vterm
PARAMETER
Single-ended HIGH level output voltage
Single-ended LOW level output voltage
Single-ended output voltage swing
Change in steady-state common-mode
output voltage between logic states
Peak-to-peak output differential voltage
Single-ended standby output voltage
Single-ended power down output current
Short circuit output current
Input termination impedance
Input termination voltage
TEST CONDITIONS
AVCC = 3.3 V, RT = 50 Ω
AVCC = 3.3 V, RT = 50 Ω,
LP = 0
0 V ≤ VCC ≥ 1.5 V, AVCC = 3.3 V,
RT = 50 Ω
VID = 500 mV
MIN
AVCC–10
AVCC–600
400
–5
800
AVCC–10
TYP
MAX
AVCC+10
AVCC–400
600
UNIT
mV
mV
mV
5 mV
1200 mV
AVCC+10 mV
–10
–15
45
50
1
10 µA
15 mA
55 Ω
2V
SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
tPLH
tPHL
tR
tF
tSK(P)
tSK(D)
tSK(O)
tJITD(PP)
tJITC(PP)
Propagation delay time
Propagation delay time
Rise time
Fall time
Pulse skew
Intra-pair skew
Inter-pair skew
Peak-to-peak output residual data jitter
Peak-to-peak output residual clock jitter
TEST CONDITIONS
AVCC = 3.3 V, RT = 50 Ω, f = 1 MHz
AVCC = 3.3 V, RT = 50 Ω, dR = 2.5 Gbps
AVCC = 3.3 V, RT = 50 Ω, f = 250 MHz
MIN TYP
250 350
250 350
60
90
60
90
8
20
20
14
8
MAX
600
600
140
140
15
40
65
50
30
UNIT
ps
ps
ps
ps
ps
ps
ps
ps
ps
12
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