PCI1221 Datasheet, PDF (12/123 Pages) Texas Instruments – PC CARD CONTROLLERS

PCI1221 GHK/PDV
PC CARD CONTROLLERS
SCPS042 – JULY 1998
Terminal Functions
The terminals are grouped in tables by functionality, such as PCI system function, power-supply function, etc. The
terminal numbers are also listed for convenient reference.
power supply
NAME
GND
TERMINAL
PDV NUMBER
GHK NUMBER
13, 22, 44, 75, 96, 129, 153, G2, J5, P2, P9, V14, K18, E18,
167, 181, 194, 207
F12, B10, E8, C5
VCC
7, 31, 64, 86, 113, 143, 164,
175, 187, 201
F3, L3, U7, W12, N15, G19,
B14, A11, C9, E7
VCCA
120
M17
VCCB
38
M5
VCCI
VCCP
148
1, 178
F18
D1, E11
FUNCTION
Device ground terminals
Power supply terminal for core logic (3.3 V)
Clamp voltage for PC Card A interface. Indicates Card A
signaling environment, 5 V or 3.3 V.
Clamp voltage for PC Card B interface. Indicates Card B
signaling environment, 5 V or 3.3 V.
Clamp voltage for interrupt subsystem interface and
miscellaneous I/O. (5 V or 3.3 V)
Clamp voltage for PCI signaling (5 V or 3.3 V)
PC Card power switch
TERMINAL
NAME
PIN NUMBER
PDV GHK
CLOCK 151 E19
DATA
152 F14
LATCH 150 F17
I/O
TYPE
I/O
O
O
FUNCTION
Three-line power switch clock. Information on the DATA line is sampled at the rising edge of CLOCK.
CLOCK defaults to an input, but can be changed to a PCI1221 output by using the P2CCLK bit in the
System Control Register. The TPS2206 defines the maximum frequency of this signal to be 2 MHz.
If a system design defines this terminal as an output, then this terminal requires an external pull down
resister. The frequency of the PCI1221 output CLOCK is derived from dividing the PCI CLK by 36.
Three-line power switch data. DATA is used to serially communicate socket power control information
to the power switch.
Three-line power switch latch. LATCH is asserted by the PCI1221 to indicate to the PC Card power
switch that the data on the DATA line is valid. When a pulldown resistor is implemented on this
terminal, the MFUNC4 and MFUNC1 terminals provide the serial EEPROM SCL and SDA interface.
PCI system
TERMINAL
NAME
PIN NUMBER
PDV GHK
I/O
TYPE
PCLK
180 A10
I
PRST
166 A14
I
FUNCTION
PCI bus clock. PCLK provides timing for all transactions on the PCI bus. All PCI signals are sampled at
the rising edge of PCLK.
PCI reset. When the PCI bus reset is asserted, PRST causes the PCI1221 to place all output buffers
in a high-impedance state and reset all internal registers. When PRST is asserted, the device is
completely nonfunctional. After PRST is deasserted, the PCI1221 is in its default state.
When the SUSPEND and PRST are asserted, the device is protected from the PRST clearing the internal
registers. All outputs are placed in a high-impedance state, but the contents of the registers are
preserved.
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