CDCE949_10 Datasheet, PDF (12/31 Pages) Texas Instruments – Programmable 4-PLL VCXO Clock Synthesizer with 1.8V, 2.5V and 3.3V LVCMOS Outputs

CDCE949
CDCEL949
SCAS844D – AUGUST 2007 – REVISED MARCH 2010
Table 6. Command Code Definition
BIT
7
(6:0)
DESCRIPTION
0 = Block Read or Block Write operation
1 = Byte Read or Byte Write operation
Byte Offset for Byte Read, Block Read, Byte Write and Block Write operation.
Generic Programming Sequence
1
7
S
Slave Address
MSB
11
8
R/W A
Data Byte
LSB MSB
11
AP
LSB
S Start Condition
Sr Repeated Start Condition
R/W 1 = Read (Rd) from CDCE9xx device; 0 = Write (Wr) to the CDCE9xxx
A Acknowledg (ACK = 0 and NACK =1)
P Stop Condition
Master to Slave Transmission
Slave to Master Transmission
Figure 7. Generic Programming Sequence
www.ti.com
Byte Write Programming Sequence
1
7
11
8
1
S
Slave Address
Wr A
CommandCode
A
Figure 8. Byte Write Protocol
8
Data Byte
11
AP
Byte Read Programming Sequence
1
7
11
S
Slave Address
Wr A
8
CommandCode
11
AS
8
Data Byte
11
AP
Figure 9. Byte Read Protocol
7
Slave Address
11
Rd A
Block Write Programming Sequence
1
7
11
8
1
8
1
S
Slave Address
Wr A
CommandCode
A
Byte Count = N
A
8
1
Data Byte 0
A
8
Data Byte 1
1
A
…
8
Data Byte N-1
11
AP
NOTE: Data Byte 0 Bits [7:0] is reserved for Revision Code and Vendor Identification. Also it is used for internal test purpose
and should not be overwritten.
Figure 10. Block Write Programming
12
Submit Documentation Feedback
Copyright © 2007–2010, Texas Instruments Incorporated
Product Folder Link(s): CDCE949 CDCEL949