BUF08821 Datasheet, PDF (12/27 Pages) Texas Instruments – Programmable Gamma-Voltage Generator and VCOM Calibrator with Integrated Two-Bank Memory

SBOS438C – AUGUST 2008 – REVISED AUGUST 2009 ................................................................................................................................................. www.ti.com
The process of updating multiple DAC/V_COM registers
begins the same as when updating a single register.
However, instead of sending a STOP condition after
writing the addressed register, the master continues
to send data for the next register. The BUF08821
automatically and sequentially steps through
subsequent registers as additional data are sent. The
process continues until all desired registers have
been updated or a STOP or START condition is sent.
To write to multiple DAC/V_COM registers:
1. Send a START condition on the bus.
2. Send the device address and read/write bit =
LOW. The BUF08821 acknowledges this byte.
3. Send either the OUT1 pointer address byte to
start at the first DAC, or send the pointer address
byte for whichever DAC/V_COM is the first in the
sequence of DACs/V_COM to be updated. The
BUF08821 begins with this DAC/V_COM and steps
through subsequent DACs/V_COM in sequential
order.
4. Send the bytes of data; begin by sending the
most significant byte (bits D15–D8, of which only
bits D9 and D8 have meaning, and bits D15–D14
must not be 01), followed by the least significant
byte (bits D7–D0). The first two bytes are for the
DAC/V_COM addressed in the previous step. The
DAC/V_COM register is automatically updated after
receiving the second byte. The next two bytes are
for the following DAC/V_COM. That DAC/V_COM
register is updated after receiving the fourth byte.
This process continues until the registers of all
following DACs/V_COM have been updated. The
BUF08821 will continue to accept data for a total
of 18 DACs; however, the ten data sets following
the 8th data set will be meaningless. The 19th
data set will apply to V_COM. The write disable bit
cannot be accessed using this method. It must be
written to using the write to a single DAC register
procedure.
5. Send a STOP or START condition on the bus.
The BUF08821 acknowledges each byte. To
terminate communication, send a STOP or START
condition on the bus. Only DAC registers that have
received both bytes of data are updated.
Reading: DAC/V_COM/OTHER Register (Volatile
Memory)
Reading a register returns the data stored in that
DAC/V_COM/OTHER register.
To read a single DAC/V_COM/OTHER register:
1. Send a START condition on the bus.
2. Send the device address and read/write bit =
LOW. The BUF08821 acknowledges this byte.
3. Send the DAC/V_COM/OTHER pointer address
byte. Set bit D7 = 0 and D6 = 0; bits D5–D0 are
the DAC/V_COM/OTHER address. The BUF08821
acknowledges, stores, and returns data only from
these addresses:
– 000000 through 000111
– 010010
– 111100 through 111111
See Table 4 for valid DAC/V_COM/OTHER
addresses.
4. Send a START or STOP/START condition.
5. Send the correct device address and read/write
bit = HIGH. The BUF08821 acknowledges this
byte.
6. Receive two bytes of data. They are for the
specified register. The most significant byte (bits
D15–D8) is received first; next is the least
significant byte (bits D7–D0). In the case of
DAC/V_COM channels, bits D15–D10 have no
meaning.
7. Acknowledge after receiving the first byte.
8. Send a STOP or START condition on the bus or
do not acknowledge the second byte to end the
read transaction.
Communication may be terminated by sending a
premature STOP or START condition on the bus, or
by not acknowledging.
To read multiple registers:
1. Send a START condition on the bus.
2. Send the device address and read/write bit =
LOW. The BUF08821 acknowledges this byte.
3. Send either the OUT1 pointer address byte to
start at the first DAC, or send the pointer address
byte for whichever register is the first in the
sequence of DACs/V_COM to be read. The
BUF08821 begins with this DAC/V_COM and steps
through subsequent DACs/V_COM in sequential
order.
4. Send a START or STOP/START condition on the
bus.
5. Send the correct device address and read/write
bit = HIGH. The BUF08821 acknowledges this
byte.
6. Receive two bytes of data. They are for the
specified DAC/V_COM. The first received byte is the
most significant byte (bits D15–D8, only bits D9
and D8 have meaning), next is the least
significant byte (bits D7–D0).
7. Acknowledge after receiving each byte of data.
8. When all desired DACs have been read, send a
STOP or START condition on the bus.
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