ADS8364 Datasheet, PDF (12/22 Pages) Texas Instruments – 250kHz, 16-Bit, 6-Channel Simultaneous Sampling ANALOG-TO-DIGITAL CONVERTERS

current into the ADS8364 charges the internal capacitor
array during the sampling period. After this capacitance has
been fully charged, there is no further input current. The
source of the analog input voltage must be able to charge the
input capacitance (25pF) to a 16-bit settling level within 3
clock cycles if the minimum acquisition time is used. When
the converter goes into the hold mode, the input impedance
is greater than 1GΩ.
Care must be taken regarding the absolute analog input
voltage. The +IN and –IN inputs should always remain within
the range of AGND – 0.3V to AV_DD + 0.3V.
TRANSITION NOISE
The transition noise of the ADS8364 itself is low,
as shown in Figure 5. These histograms were generated by
applying a low-noise DC input and initiating 8000 conversions.
The digital output of the ADC will vary in output code due to
the internal noise of the ADS8364. This is true for all 16-bit,
SAR-type ADCs. Using a histogram to plot the output codes,
the distribution should appear bell-shaped with the peak of the
bell curve representing the nominal code for the input value.
The ±1σ, ±2σ, and ±3σ distributions will represent the 68.3%,
95.5%, and 99.7%, respectively, of all codes. The transition
noise can be calculated by dividing the number of codes
measured by 6 and this will yield the ±3σ distribution, or
99.7%, of all codes. Statistically, up to three codes could fall
outside the distribution when executing 1000 conversions.
Remember, to achieve this low-noise performance, the peak-
to-peak noise of the input signal and reference must be
< 50µV.
2726
813
720
1183
930
906
680
167
0
67
0
32803 32804 32805 32806 32807 32808 32809 32810 32811 32812 32813
Code
FIGURE 5. 8000 Conversion Histogram of a DC Input.
BIPOLAR INPUTS
The differential inputs of the ADS8364 were designed to accept
bipolar inputs (–V_REF and +V_REF) around the common-mode
voltage (2.5V), which corresponds to a 0V to 5V input range with
a 2.5V reference. By using a simple op amp circuit featuring
four, high-precision external resistors, the ADS8364 can be
configured to accept bipolar inputs. The conventional ±2.5V,
±5V, and ±10V input ranges could be interfaced to the ADS8364
using the resistor values shown in Figure 6.
Bipolar Input
4kΩ
20kΩ
R₁
OPA227
R₂
1.2kΩ
1.2kΩ
+IN
–IN
ADS8364
OPA227
REF_OUT (pin 61)
2.5V
BIPOLAR INPUT
R₁
±10V
1kΩ
±5V
2kΩ
±2.5V
4kΩ
R₂
5kΩ
10kΩ
20kΩ
FIGURE 6. Level Shift Circuit for Bipolar Input Ranges.
TIMING AND CONTROL
The ADS8364 uses an external clock (CLK, pin 28) which
controls the conversion rate of the CDAC. With a 5MHz
external clock, the ADC sampling rate is 250kHz which
corresponds to a 4µs maximum throughput time. Acquistion
and conversion takes a total of 20 clock cycles.
THEORY OF OPERATION
The ADS8364 contains six 16-bit ADCs that can operate
simultaneously in pairs. The three hold signals (HOLDA,
HOLDB, and HOLDC) initiate the conversion on the specific
channels. A simultaneous hold on all six channels can occur
with all three hold signals strobe together. The converted
values are saved in six registers. For each read operation,
the ADS8364 outputs 16 bits of information (16 Data or 3
Channel Address, Data Valid, and some synchronization
information). The Address/Mode signals (A0, A1, and A2)
select how the data is read from the ADS8364. These
Address/Mode signals can define a selection of a single
channel, a cycle mode that cycles through all channels, or a
FIFO mode that sequences the data determined by the order
of the hold signals. The FIFO mode will allow the six registers
to be used by a single-channel pair and, therefore, three
locations for CH X0 and three locations for CH X1 can be
updated before they are read from the part.
EXPLANATION OF CLOCK, RESET, FD, AND EOC PINS
Clock—An external clock has to be provided for the ADS8364.
The maximum clock frequency is 5MHz. The minimum clock
cycle is 200ns (Timing Diagram, t_C1), and the clock has to remain
HIGH (Timing Diagram, t_W1) or LOW for at least 60ns.
RESET—Bringing reset signal LOW will reset the ADS8364.
It will clear all the output registers, stop any actual conver-
sions, and will close the sampling switches. The reset signal
has to stay LOW for at least 20ns (see Figure 7, t_W4). The
reset signal should be back HIGH for at least 20ns (see
Figure 7, t_D2), before starting the next conversion (negative
hold edge).
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ADS8364
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