ADS7924 Datasheet, PDF (12/42 Pages) Texas Instruments – 2.2V, 12-Bit, 4-Channel, microPOWER™ ANALOG-TO-DIGITAL CONVERTER WITH I2C INTERFACE

ADS7924
SBAS482A – JANUARY 2010 – REVISED MAY 2010
ALARM
The ADS7924 offers an independent alarm function
for each input channel. An 8-bit window comparator
can be enabled to test the ADC conversion result
against an upper limit set by the ULR register and
against a lower limit set by the LLR register. If the
conversion result is less than or equal to the LLR
threshold value or greater than or equal to the ULR
threshold value, the comparator is tripped. There are
separate upper and lower registers for each input
channel.
A programmable counter determines how many
comparator trips it takes to generate an alarm. A
separate counter is used for each channel and is
incremented whenever the comparator trips, either for
the upper or lower thresholds. That is, an ADC
conversion result on channel 1 that exceeds the ULR
threshold or falls below the LLR threshold increments
the counter for that channel. Figure 22 shows a
conceptual diagram of the window comparator and
alarm circuitry.
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When an alarm occurs, the INT pin can be configured
to generate an interrupt. The channel that generated
the alarm can be read from the registers. A read of
the Interrupt Control register clears the alarm register
and also resets the alarm counter.
ADC OPERATING MODES
The ADS7924 offers multiple operating modes to
support a wide variety of monitoring needs.
Conversions can either be started manually or set to
automatically continue. The mode is set by writing to
the MODE register, and changes take effect as soon
as the write completes. Table 2 gives a brief
description of each mode.
Idle Mode
Use this mode to save power when not converting. All
circuits are shut down.
Awake Mode
All circuits are operating in this mode and the ADC is
ready to convert. When switching between modes, be
sure to first select the Awake mode and then switch
to the desired mode. This procedure ensures the
internal control logic is properly synchronized.
ADC
Upper Limit Threshold
ULRx[7:0]⁽²⁾
CHX Data
Window
Comparator
X⁽²⁾
LLRx[7:0]
Lower Limit Threshold
ALMCNT[2:0]⁽¹⁾
Counter X
Alarm for
Channel X
(1) The same ALMCNT value is used for all four window comparators.
(2) X = 0 to 3.
Figure 22. Window Comparator/Alarm Conceptual Block Diagram
Table 2. Mode Descriptions
MODE
DESCRIPTION
Idle
All circuits shutdown; lowest power setting
Awake
All circuits awake and ready to convert
Manual-Single
Select input channel is converted once
Manual-Scan
All input channels are converted once
Auto-Single
One input channel is continuously converted
Auto-Scan
All input channels are continuously converted
Auto-Single with Sleep One input channel is continuously converted with programmable sleep time between conversions
Auto-Scan with Sleep All input channels are continuously converted with programmable sleep time between conversions
Auto-Burst Scan with
Sleep
All input channels are converted with minimal delay followed by a programmable sleep time
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