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ADS7841EG4 Datasheet, PDF (12/19 Pages) Texas Instruments – 12-Bit, 4-Channel Serial Output Sampling ANALOG-TO-DIGITAL CONVERTER
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Digital Timing
Figure 5 and Tables VI and VII provide detailed timing for
the digital interface of the ADS7841.
15-Clocks per Conversion
Figure 6 provides the fastest way to clock the ADS7841.
This method will not work with the serial interface of most
microcontrollers and digital signal processors as they are
generally not capable of providing 15 clock cycles per serial
transfer. However, this method could be used with Field
Programmable Gate Arrays (FPGAs) or Application Spe-
cific Integrated Circuits (ASICs). Note that this effectively
increases the maximum conversion rate of the converter
beyond the values given in the specification tables, which
assume 16 clock cycles per conversion.
SYMBOL
DESCRIPTION
MIN TYP MAX UNITS
tACQ
Acquisition Time
1.5
tDS
DIN Valid Prior to DCLK Rising 100
tDH
DIN Hold After DCLK HIGH
10
tDO
DCLK Falling to DOUT Valid
tDV
CS Falling to DOUT Enabled
tTR
CS Rising to DOUT Disabled
tCSS
CS Falling to First DCLK Rising 100
tCSH
CS Rising to DCLK Ignored
0
tCH
DCLK HIGH
200
tCL
DCLK LOW
200
tBD
DCLK Falling to BUSY Rising
tBDV
CS Falling to BUSY Enabled
tBTR
CS Rising to BUSY Disabled
µs
ns
ns
200
ns
200
ns
200
ns
ns
ns
ns
ns
200
ns
200
ns
200
ns
TABLE VI. Timing Specifications (+VCC = +2.7V to 3.6V,
TA = –40°C to +85°C, CLOAD = 50pF).
SYMBOL
DESCRIPTION
MIN TYP MAX UNITS
tACQ
Acquisition Time
900
tDS
DIN Valid Prior to DCLK Rising 50
tDH
DIN Hold After DCLK HIGH
10
tDO
DCLK Falling to DOUT Valid
tDV
CS Falling to DOUT Enabled
tTR
CS Rising to DOUT Disabled
tCSS
CS Falling to First DCLK Rising 50
tCSH
CS Rising to DCLK Ignored
0
tCH
DCLK HIGH
150
tCL
DCLK LOW
150
tBD
DCLK Falling to BUSY Rising
tBDV
CS Falling to BUSY Enabled
tBTR
CS Rising to BUSY Disabled
ns
ns
ns
100
ns
70
ns
70
ns
ns
ns
ns
ns
100
ns
70
ns
70
ns
TABLE VII. Timing Specifications (+VCC = +4.75V to
+5.25V, TA = –40°C to +85°C, CLOAD = 50pF).
CS
DCLK
DIN
BUSY
DOUT
tCSS
tCH
tDS
tBDV
tDV
tCL
tBD
tBD
tD0
tDH
PD0
11
10
tCSH
tBTR
tTR
FIGURE 5. Detailed Timing Diagram.
CS
DCLK
DIN
BUSY
1
S
A2
A1
A0
MODE
SGL/
DIF
PD1
PD0
15 1
S
A2
A1
A0
MODE
SGL/
DIF
PD1
PD0
15 1
S A2 A1 A0
DOUT
11 10 9 8 7 6 5 4 3 2 1 0
FIGURE 6. Maximum Conversion Rate, 15-Clocks per Conversion.
12
11 10 9 8 7 6 5 4 3 2
ADS7841
SBAS084B
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