CC2510FX_10 Datasheet, PDF (112/244 Pages) Texas Instruments – Low-Power SoC (System-on-Chip) with MCU, Memory, 2.4 GHz RF Transceiver, and USB Controller

The polarity of the PWM signal is determined
by whether output compare mode 3 or 4 is
used.
Centre-aligned: PWM outputs can be
generated when the timer up/down mode is
selected. The channel output compare mode 3
CC2510Fx / CC2511Fx
or 4 (defined by T1CCTLn.CMP bits, where n is
1 or 2) is selected depending on required
polarity of the PWM signal (see Figure 34).
The period of the PWM signal is determined by
T1CC0 and the duty cycle for the channel
output is determined by T1CCn (n = 1 or 2).
Figure 32: Output Compare Modes, Timer Free-running Mode
SWRS055F
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