TMS320VC5420 Datasheet, PDF (11/77 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSOR

TMS320VC5420
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS080C – MARCH 1999 – REVISED APRIL 2000
Signal Descriptions (Continued)
NAME
READY
TYPE†
DESCRIPTION
MEMORY CONTROL SIGNALS (CONTINUED)
Data-ready input signal. READY indicates that the external device is prepared for a bus transaction to be
completed. If the device is not ready (READY = 0), the processor waits one cycle and checks READY again. The
I
processor performs the READY detection if at least two software wait states are programmed.
This pin is also multiplexed with the HPI, and functions as the Host-port data ready (output) in HPI mode. Refer
to the HPI section of this table for details on the secondary function of this pin.
Read/write output signal. R/W indicates transfer direction during communication to an external device. R/W is
normally in the read mode (high), unless it is asserted low when the DSP performs a write operation.
R/W
O This pin is also multiplexed with the HPI, and functions as the Host-port Read/write input in HPI mode. Refer to
the HPI section of this table for details on the secondary function of this pin.
This pin is placed into the high-impedance state when OFF is low.
I/O space memory strobe. External I/O space is accessible by the CPU and not the direct memory access (DMA)
controller. The DMA has its own dedicated I/O space that is not accessible by the CPU.
IOSTRB
O
This pin is also multiplexed with the general pupose I/O feature, and functions as the A_GPIO3(A_TOUT) signal
in HPI mode. Refer to the general purpose I/O section of this table for details on the secondary function of this
pin.
This pin is placed into the high-impedance state when OFF is low.
The SELA/B pin designates which DSP subsystem has access to the parallel-port interface. Furthermore, this
pin determines which subsystem is accessible by the host via the HPI.
SELA/B
For external memory accesses (XIO pin high), when SELA/B is low subsystem A has control of the external
memory interface. Similarly, when SELA/B is high subsystem B has control.
I
See Table 7 for a truth table of SELA/B, HMODE and XIO pins and functionality.
At device reset, the logic combination of the XIO, HMODE, and SELA/B pin levels determines the initialization
value of the MP/MC bit (a bit in the processor mode status (PMST) register ) Refer to the memory section for
details.
CLOCKING SIGNALS
A_CLKOUT
B_CLKOUT
CLKIN§
Master clock output signal. CLKOUT cycles at the machine-cycle rate of the CPU. The internal machine cycle
O is bounded by the falling edges of this signal. The CLKOUT pin can be turned off by writing a “1” to the CLKOFF
bit of the PMST register. CLKOUT goes into the high-impedance state when EMU1/OFF is low.
I
Input clock to the device. CLKIN connects to an oscillator circuit/device.
VCO
O
VCO is the output of the voltage-controlled oscillator stage of the PLL. This is a 3-state output during normal
operation. Active in silicon test/debug mode.
MULTICHANNEL BUFFERED SERIAL PORT 0, 1, AND 2 SIGNALS
A_BCLKR0‡§
B_BCLKR0‡§
A_BCLKR1‡§
B_BCLKR1‡§
A_BCLKR2‡§
B_BCLKR2‡§
I/O/Z
Receive clocks. BCLKR serves as the serial shift clock for the buffered serial-port receiver. Input from an external
clock source for clocking data into the McBSP. When not being used as a clock, these pins can be used as
general-purpose I/O by setting RIOEN = 1.
BCLKR can be configured as an output by the way of the CLKRM bit in the PCR register.
† _{I = Input, O = Output, S = Supply, Z = High Impedance}
‡ _{This pin has an internal pullup resistor.}
§ _{These pins have Schmitt trigger inputs.}
¶ _{This pin has an internal bus holder controlled by way of the BSCR register in subchip A.}
# _{This pin is used by Texas Instruments for device testing and should be left unconnected.}
|| _{This pin has an internal pulldown resistor.}
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