TLV320AIC26_08 Datasheet, PDF (11/67 Pages) Texas Instruments – LOW POWER STEREP AUDIO CODEC WITH HEADPHONE / SPEAKER AMPLIFIER AND 12-BIT BATTERY / TEMPERATURE / AUXILIARY ADC

www.ti.com
TLV320AIC26
SLAS412− DECEMBER 2003
LRCK/ADWS
BCLK
DOUT
DIN
tH(BCLK)
th(WS)
tL(BCLK)
tP(BCLK)
tS (WS)
th(WS)
td(DO−BCLK)
ts (DI)
tS (WS)
th (DI)
Figure 4. DSP Timing in Slave Mode
TYPICAL TIMING REQUIREMENTS (FIGURE 4)
All specifications at 25°C, DVDD = 1.8 V ⁽¹⁾
PARAMETER
tH (BCLK)
BCLK high period
tL (BCLK)
BCLK low period
ts(WS)
ADWS/LRCK setup
th(WS)
ADWS/LRCK hold
td (DO−BCLK) BCLK to DOUT delay
ts(DI)
DIN setup
th(DI)
DIN hold
tr
Rise time
tf
Fall time
(1) _{These parameters are based on characterization and are not tested in production.}
IOVDD = 1.1 V
MIN MAX
35
35
6
6
25
6
6
5
5
IOVDD = 3.3 V
MIN MAX
35
35
6
6
15
6
6
4
4
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
11