TAS5414_0705 Datasheet, PDF (11/44 Pages) Texas Instruments – FOUR-CHANNEL AUTOMOTIVE DIGITAL AMPLIFIERS

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TAS5414
TAS5424
SLOS514 – FEBRUARY 2007
TIMING REQUIREMENTS FOR I²C INTERFACE SIGNALS
over recommended operating conditions (unless otherwise noted)
PARAMETER
t_r
Rise time for both SDA and SCL signals
t_f
Fall time for both SDA and SCL signals
t_w(H)
SCL pulse duration, high
t_w(L)
SCL pulse duration, low
t_su2
Setup time for START condition
t_h2
START condition hold time after which first clock pulse is generated
t_su1
Data setup time
t_h1
Data hold time
t_su3
Setup time for STOP condition
C_B
Load capacitance for each bus line
MIN TYP
4
4.7
4.7
4
250
0 ⁽¹⁾
4
MAX
1000
300
400
UNIT
ns
ns
µs
µs
µs
µs
ns
ns
µs
pF
(1) A device must internally provide a hold time of at least 300 ns for the SDA signal to bridge the undefined region of the falling edge of
SCL.
t_w(H)
t_w(L)
t_r
t_f
SCL
SDA
SCL
SDA
t_su1
t_h1
Figure 1. SCL and SDA Timing
T0027-01
t_h2
t_su2
t_(buf)
t_su3
Start
Condition
Stop
Condition
Figure 2. Timing for Start and Stop Conditions
T0028-01
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