TAS5100A_07 Datasheet, PDF (11/20 Pages) Texas Instruments – TRUE DIGITAL AUDIO AMPLIFIER TAS5100A PWM POWER OUTPUT STAGE

TAS5100A
SLES030 − FEBRUARY 2002
static digital specifications
RESET, PWDN, PWM_AP, PWM_AM, PWM_BP, PWM_BM, T_A = 25°C, DVDD = 3.3 V
PARAMETERS
High-level input voltage, VIH
Low-level input voltage, VIL
Input leakage current
MIN MAX UNIT
2
V
0.8 V
−10
10 µA
ERR0, ERR1, SHUTDOWN, (open drain with internal pullup resistor) T_A = 25°C, DVDD = 3.3 V)
PARAMETERS
MIN MAX
Internal pullup resistors from SHUTDOWN, ERR0, ERR1 to DVDD
15
Low-level output voltage (IO = 4 mA), VOL
0.4
UNIT
kΩ
V
TAS5000/TAS5100A system performance measured at the speaker terminals
See the TI Literature Number SLAA117 for TAS5000/TAS5100A system performance.
electrical characteristics
supply, T_A = 25°C (F_switching = 384 kHz, OUTPUTA and OUTPUTB not connected, DVDD = 3.3 V,
PVDDA1 = 25 V, PVDDB1 = 25 V, PVDDA2 = 22 V, PVDDB2 = 22 V, 50% input duty cycle)
PARAMETER
Supply current
DVDD
PVDDA1
PVDDB1
Operating
PWDN = 0
Operating†
PWDN = 0
PVDDA2
Operating
PVDDB2
PWDN = 0
† _{13-kΩ resistor from BIAS_A (pin 11) to DVSS and 13-kΩ resistor from BIAS_B (pin 12) to DVSS.}
TYP MAX UNIT
2
mA
500 µA
6.3
mA
25 µA
6.5
mA
250 µA
H-Bridge transistors, PVDDA2 = PVDDB2 = 22 V, DVDD = 3.3 V, T_A = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
Drain-to-source breakdown voltage
ID = 1 mA,
PWDN = 0, Hi-Z state
28
V
Forward on-state resistance, low side drivers
OUTPUTA and OUTPUTB to PVSS
ISINK = 2.5 A,
PWM_AP = PWM_BP = 0,
See Notes 2, 3, and 4, PWM_AM = PWM_BM = 1
0.2
Ω
Forward on-state resistance, high side drivers
ISOURCE = 2.5 A,
PWM_AP = PWM_BP = 1,
PVDDA1 to OUTPUTA, PVDDB1 to OUTPUTB See Notes 2, 3, and 5, PWM_AM = PWM_BM = 0
0.2
Ω
On-state resistance matching low-side drivers
98%
On-state resistance matching high-side drivers
98%
NOTES:
1. Test time should be < 1 ms to avoid temperature change.
2. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts.
3. Connect PVDDA2 and PVDDB2 to 22-V power supply with respect to PVSS. LDROUTA, LDROUTB, BOOTSTRAPA, and
BOOTSTRAPB pins open.
4. Connect PVDDA2 to 22-V power supply with respect to PVSS. LDROUTA, LDROUTB, BOOTSTRAPA and BOOTSTRAPB
capacitors are connected respectively. Clock PWM inputs to allow bootstrap capacitors to charge. 93−99% modulation must be used
on PWM_AP, PWM_AM, PWM_BP, and PWM_BM inputs to prevent the activity detector from shutting down the device during this
measurement. Note that Fswitching = 384 kHz.
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