SN65DSI83 Datasheet, PDF (11/34 Pages) Texas Instruments – MIPI DSI BRIDGE TO FLATLINK LVDS Single Channel DSI to Single-Link LVDS Bridge

SN65DSI83
www.ti.com
SLLSEC1D – SEPTEMBER 2012 – REVISED DECEMBER 2012
DEVICE INFORMATION
Reset Implementation
When EN is de-asserted (low), the SN65DSI83 is in SHUTDOWN or RESET state. In this state, CMOS inputs
are ignored, the MIPI® D-PHY inputs are disabled and outputs are high impedance. It is critical to transition the
EN input from a low to a high level after the V_CC supply has reached the minimum operating voltage as shown in
Figure 7. This is achieved by a control signal to the EN input, or by an external capacitor connected between EN
and GND.
V_CC
1.65V
EN
t_VCC
t_en
Figure 7. Cold Start V_CC Ramp up to EN
When implementing the external capacitor, the size of the external capacitor depends on the power up ramp
of the V_CC supply, where a slower ramp-up results in a larger value external capacitor. See the latest
reference schematic for the SN65DSI83 device and, or consider approximately 200 nF capacitor as a
reasonable first estimate for the size of the external capacitor.
Both EN implementations are shown in Figure 8 and Figure 9.
V_CC
GPO
EN
EN
C
R_EN =200 kΩ
C
SN65DSI83
controller
SN65DSI83
Figure 8. External Capacitor Controlled EN
Figure 9. EN Input from Active Controller
When the SN65DSI83 is reset while V_CC is high, the EN pin must be held low for at least 10 ms before being
asserted high as shown in Figure 5 to be sure that the device is properly reset. The DSI lanes including the CLK
lanes MUST be driven to LP11 while the device is in reset until the EN pin is asserted high per the timing shown
in Figure 5.
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: SN65DSI83
Submit Documentation Feedback
11