LP38858_15 Datasheet, PDF (11/21 Pages) Texas Instruments – 1.5A Fast-Response High-Accuracy LDO Linear Regulator with Soft-Start

LP38858
www.ti.com
SNVS462D – OCTOBER 2006 – REVISED APRIL 2013
Soft-Start Time = C_SS × r_SS × 5
(1)
Since the V_OUT rise will be exponential, not linear, the in-rush current will peak during the first time constant (τ),
and V_OUT will require four additional time constants (4τ) to reach the final value (5τ) .
After achieving normal operation, should V_BIAS fall below the ULVO threshold the device output will be disabled
and the Soft-Start capacitor (C_SS) discharge circuit will become active. The C_SS discharge circuit will remain
active until V_BIAS falls to 500 mV (typical). When V_BIAS falls below 500 mV (typical), the C_SS discharge circuit will
cease to function due to a lack of sufficient biasing to the control circuitry.
Since V_REF appears on the SS pin, any leakage through C_SS will cause V_REF to fall, and thus affect V_OUT. A
leakage of 50 nA (about 10 MΩ) through C_SS will cause V_OUT to be approximately 0.1% lower than nominal, while
a leakage of 500 nA (about 1 MΩ) will cause V_OUT to be approximately 1% lower than nominal. Typical ceramic
capacitors will have a factor of 10X difference in leakage between 25°C and 85°C, so the maximum ambient
temperature must be included in the capacitor selection process.
Typical C_SS values will be in the range of 1 nF to 100 nF, providing typical Soft-Start times in the range of 70 μs
to 7 ms (5τ). Values less than 1 nF can be used, but the Soft-Start effect will be minimal. Values larger than 100
nF will provide soft-start, but may not be fully discharged if V_BIAS falls from the UVLO threshold to less than 500
mV in less than 100 µs.
Figure 27 shows the relationship between the C_OUT value and a typical C_SS value.
Figure 27. Typical C_SS vs C_OUT Values
The C_SS capacitor must be connected to a clean ground path back to the device ground pin. No components,
other than C_SS, should be connected to the SS pin, as there could be adverse effects to V_OUT.
If the Soft-Start function is not needed the SS pin should be left open, although some minimal capacitance value
is always recommended.
POWER DISSIPATION AND HEAT-SINKING
Additional copper area for heat-sinking may be required depending on the maximum device dissipation (P_D) and
the maximum anticipated ambient temperature (T_A) for the device. Under all possible conditions, the junction
temperature must be within the range specified under operating conditions.
The total power dissipation of the device is the sum of three different points of dissipation in the device.
The first part is the power that is dissipated in the NMOS pass element, and can be determined with the
formula:
P_D(PASS) = (V_IN - V_OUT) × I_OUT
(2)
The second part is the power that is dissipated in the bias and control circuitry, and can be determined with the
formula:
P_D(BIAS) = V_BIAS × I_GND(BIAS)
where
• I_GND(BIAS) is the portion of the operating ground current of the device that is related to V_BIAS
(3)
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