DP83620SQ Datasheet, PDF (11/105 Pages) Texas Instruments – DP83620 Industrial Temperature Single Port 10/100 Mbps Ethernet Physical Layer

DP83620
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Signal Name
AN_EN
AN1
AN0
CLK_OUT_EN
FX_EN_Z
LED_CFG
MII_MODE
PCF_EN
RMII_MAS
Pin Name
LED_LINK
LED_SPEED/FX_S
D
LED_ACT
CLK_OUT_EN
RX_ER
CRS/CRS_DV
RX_DV
PCF_EN
TXD_3
SNLS339C – JANUARY 2011 – REVISED APRIL 2013
Type
S, O, PU
S, O, PU
S, O, PU
S, I, PD
S, O, PU
S, O, PU
S, O, PD
S, I, PD
S, I, PD
Pin #
28
27
26
21
41
40
39
22
6
Description
AUTO-NEGOTIATION ENABLE: When high, this enables Auto-
Negotiation with the capability set by AN0 and AN1 pins. When low, this
puts the part into Forced Mode with the capability set by AN0 and AN1
pins.
AN0 / AN1: These input pins control the forced or advertised operating
mode of the DP83620 according to the following table. The value on
these pins is set by connecting the input pins to GND (0) or V_CC (1)
through 2.2 kΩ resistors. These pins should NEVER be connected
directly to GND or V_CC.
The value set at this input is latched into the DP83620 at Hardware-
Reset.
The float/pull-down status of these pins are latched into the Basic Mode
Control Register and the Auto_Negotiation Advertisement Register
during Hardware-Reset.
The default is 111 since these pins have internal pull-ups.
FIBER MODE DUPLEX SELECTION: If Fiber mode is strapped using
the FX_EN_Z pin (FX_EN_Z = 0), the AN0 strap value is used to select
half or full duplex. AN_EN and AN1 are ignored in Fiber mode since it
is 100 Mb only and does not support Auto-Negotiation. In Fiber mode,
AN1 should not be connected to any system components except the
fiber transceiver.
FX_EN_ AN_EN AN1 AN0
Z
Forced Mode
1
0
0
0 10BASE-T, Half-Duplex
1
0
0
1 10BASE-T, Full-Duplex
1
0
1
0 100BASE-TX, Half-Duplex
1
0
1
1 100BASE-TX, Full-Duplex
0
X
X
0 100BASE-FX, Half-Duplex
0
X
X
1 100BASE-FX, Full-Duplex
FX_EN_ AN_EN AN1 AN0
Z
Advertised Mode
1
1
0
0 10BASE-T, Half/Full-Duplex
1
1
0
1 100BASE-TX, Half/Full-Duplex
1
1
1
0 100BASE-TX, Full-Duplex
1
1
1
1 10BASE-T, Half/Full-Duplex,
100BASE-TX, Half/Full-Duplex
CLK_OUT OUTPUT ENABLE: When high, enables clock output on the
CLK_OUT pin at power-up.
FX ENABLE: This strapping option enables 100Base-FX (Fiber) mode.
This mode is disabled by default. An external pull-down will enable
100Base-FX mode.
LED CONFIGURATION: This strapping option determines the mode of
operation of the LED pins. Default is Mode 1. Mode 1 and Mode 2 can
be controlled via the strap option. All modes are configurable via
register access. See Table 5-3 for LED Mode Selection.
MII MODE SELECT: This strapping option determines the operating
mode of the MAC Data Interface. Default operation is MII Mode with a
value of 0 due to the internal pulldown. Strapping MII_MODE high will
cause the device to be in RMII mode of operation.
MII_MODE
MAC Interface Mode
0
MII Mode
1
RMII Mode
PHY CONTROL FRAME ENABLE: When high, allows the DP83620 to
respond to PHY Control Frames.
RMII MASTER ENABLE: When MII_MODE is strapped high, this
strapping option enables RMII Master mode, in which the DP83620
uses a 25 MHz crystal connection on X1/X2 and generates the 50 MHz
RMII reference clock. If strapped low when MII_MODE is strapped high,
default RMII operation (RMII Slave) is enabled, in which the DP83620
uses a 50 MHz oscillator input on X1 as the RMII reference clock. This
strap option is ignored if the MII_MODE strap is low.
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Pin Descriptions
11